Efficacy of empirical Ciprofloxacin or Cefixime plus Metronidazole therapy for the treatment of liver abscess: a randomized control clinical trial.

Liver abscess is a potentially life-threatening medical emergency. Prompt empirical antimicrobial with or without percutaneous aspiration or drainage is therapeutic. The rational for using empirical intravenous broad-spectrum antimicrobials upfront instead of oral Fluoroquinolone or Cephalosporin is contentious. In this double blind randomized control clinical trial 69 participants received Ciprofloxacin (500 mg q 12 hourly) and 71 participants received Cefixime (200 mg q 12 hourly) orally for 2 weeks. Both the group received oral Metronidazole (800 mg q 8 hourly) for 2 weeks and percutaneous drainage or aspiration of the abscess was done as per indication and followed-up for 8 weeks. Out of 140 participants, 89.3% (N = 125) achieved clinical cure, 59 (85.5%) in Ciprofloxacin group and 66 (93%) in Cefixime group (p = 0.154). Mean duration of antimicrobial therapy was 16.2 ± 4.3 days, 15.1 ± 4.5 days in Ciprofloxacin group and 16.0 ± 4.2 days in Cefixime group (p = 0.223). Total 15 (10.7%) participants had treatment failure, 10 (14.5%) in Ciprofloxacin group and 5 (7.0%) in Cefixime group (p = 0.154). The most common reason for treatment failure was need of prolong (> 4 weeks) antimicrobial therapy due to persistent hepatic collection requiring drainage, which was significantly (p = 0.036) higher in Ciprofloxacin (14.5%, N = 10) group, compared to the Cefixime (4.2%, N = 3) group. In conclusion, both, the Ciprofloxacin or Cefixime plus Metronidazole for duration of 2-3 weeks were efficacious as empirical oral antimicrobial regimen along with prompt percutaneous drainage or aspiration for the treatment of uncomplicated liver abscess with similar efficacy. Oral Cefixime was better than Ciprofloxacin in term of lesser chance of treatment failure due to persistent collection which is required to be investigated further in larger clinical trial.Trial registration: clinicaltrials.gov PRS ID: NCT03969758, 31/05/2019.

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits.

We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell.

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.