Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

NET-TEN: a silicon neuromorphic network for low-latency detection of seizures in local field potentials.

Objective. Therapeutic intervention in neurological disorders still relies heavily on pharmacological solutions, while the treatment of patients with drug resistance remains an unresolved issue. This is particularly true for patients with epilepsy, 30% of whom are refractory to medications. Implantable devices for chronic recording and electrical modulation of brain activity have proved a viable alternative in such cases. To operate, the device should detect the relevant electrographic biomarkers from local field potentials (LFPs) and determine the right time for stimulation. To enable timely interventions, the ideal device should attain biomarker detection with low latency while operating under low power consumption to prolong battery life.Approach. Here we introduce a fully-analog neuromorphic device implemented in CMOS technology for analyzing LFP signals in anin vitromodel of acute ictogenesis. Neuromorphic networks have progressively gained a reputation as low-latency low-power computing systems, which makes them a promising candidate as processing core of next-generation implantable neural interfaces.Main results. The developed system can detect ictal and interictal events with ms-latency and with high precision, consuming on average 3.50 nW during the task.Significance. The work presented in this paper paves the way to a new generation of brain implantable devices for personalized closed-loop stimulation for epilepsy treatment.