RESUMO
Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.
RESUMO
Assembling two-dimensional van der Waals (vdW)-layered materials into heterostructures is an exciting development that sparked the discovery of rich correlated electronic phenomena. vdW heterostructures also offer possibilities for designer device applications in areas such as optoelectronics, valley- and spintronics, and quantum technology. However, realizing the full potential of these heterostructures requires interfaces with exceptionally low disorder which is challenging to engineer. Here, we show that thermal scanning probes can be used to create pristine interfaces in vdW heterostructures. Our approach is compatible at both the material- and device levels, and monolayer WS2 transistors show up to an order of magnitude improvement in electrical performance from this technique. We also demonstrate vdW heterostructures with low interface disorder enabling the electrical formation and control of quantum dots that can be tuned from macroscopic current flow to the single-electron tunneling regime.