Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate.

In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-VTH (HVT) state and the screening of the applied field by the channel at the low-VTH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.

Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning.

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current-voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors.

In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 1012 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic '1' and '0' states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.

Neural oscillation of single silicon nanowire neuron device with no external bias voltage.

In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p-n-p-n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10-15 J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.

Integrate-and-Fire Neuron Circuit Without External Bias Voltages.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

Effect of Ge Mole Fraction on Performance of Underlapped Gate-All-Around SiGe-Source Tunneling Field-Effect Transistors.

In this paper, we propose the design optimization of underlapped Si1-xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I-V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1-xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

Steep switching characteristics of single-gated feedback field-effect transistors.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec-1, an on/off current ratio of approximately 1011, and an on-current of approximately 10-4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.