Multi-Segment TFT Compact Model for THz Applications.

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current-voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

A Low-power and Low-noise Multi-purpose Chopper Amplifier with High CMRR and PSRR.

In this article, by choosing and optimizing suitable structure in each stage, we have designed a multi-purpose low noise chopper amplifier. The proposed neural chopper amplifier with high CMRR and PSRR is suitable for EEG, LFP and AP signals while it has a low NEF. In order to minimize the noise and increase the bandwidth, a single stage current reuse amplifier with pseudo-resistor common-mode feedback is chosen, while a simple fully differential amplifier is implemented at the second stage to provide high swing. A DC servo loop with an active RC integrator is designed to block the DC offset of electrodes and a positive feedback loop is used to increase the input impedance. Finally, an area and power-efficient ripple reduction technique and chopping spike filter are used in order to have a clear signal. The designed circuit is simulated in a commercially available 0.18 µm CMOS technology. 3.7 µA current is drawn from a ±0.6V supply. The total bandwidth is from 50 mHz to 10 kHz while the total inputreferred noise in this bandwidth is 2.9 µVrms and the mid-band gain is about 40 dB. The designed amplifier can tolerate up to 60 mV DC electrode offset and the amplifier's input impedance with positive feedback loop is 17 MΩ while the chopping frequency is 20 kHz. With the designed ripple reduction, there is just a negligible peak in the input-referred noise due to upmodulated noise at chopping frequency. In order to prove the performance of the designed circuit, 500 Monte Carlo analysis is done for process and mismatch. The mean value for CMRR and PSRR are 94 and 80 dB, respectively.

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging.

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.

A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound.

Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 [Formula: see text] of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences.