Liquid Metal Oxide-Assisted Integration of High-k Dielectrics and Metal Contacts for Two-Dimensional Electronics.

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.

Effects of insertion of an h-AlN monolayer spacer in Pt-WSe2-Pt field-effect transistors.

The growth of two-dimensional hexagonal aluminum nitride (h-AlN) on transition metal dichalcogenide (TMD) monolayers exhibits superior uniformity and smoothness compared to HfO 2 on silicon substrate. This makes an h-AlN monolayer an ideal spacer between the gate oxide material and the WSe2 monolayer in a two-dimensional field effect transistor (FET). From first principles approaches, we calculate and compare the transmission functions and current densities of Pt-WSe2-Pt nanojunctions without and with the insertion of an h-AlN monolayer as a spacer in the gate architecture. The inclusion of h-AlN can alter the characteristics of the Pt-WSe2-Pt FET in response to the gate voltage ( V g ). The FET without (or with) h-AlN exhibits the characteristics of a P-type (or bipolar) transistor: an on/off ratio of around 2.5 × 10 6 (or 1.7 × 10 6 ); and an average subthreshold swing (S.S.) of approximately 109 mV/ dec. (or 112 mV/ dec. ), respectively. We observe that V g shifts the profile of the transmission function by an energy of α ( e V g ) , where α represents the gate-controlling efficiency. We observed that α in = 83 % and α out = 33 % , corresponding to whether the Fermi energy is located inside or outside the band gap. Therefore, we construct an effective gate model based on the Landauer formula, with the transmission function at V g = 0 as the baseline. Our model generates results that are consistent with those obtained through first principles calculations. The relative error in current densities between model and first-principles calculations is within [ l n ( 10 ) S . S . ] | Δ V G eff | . The 2D atomistic FETs show excellent device specifications and the ability to compete with existing transistors based on traditional silicon technology. Our findings could help advance the design of TMD-based FETs.

Engineering Steep Subthreshold Swings in High-Performance Organic Field-Effect Transistor Sensors.

Organic field-effect transistor (OFET)-based sensors have gained considerable attention for information perception and processing in developing artificial intelligent systems owing to their amplification function and multiterminal regulation. Over the last few decades, extensive research has been conducted on developing OFETs with steep subthreshold swings (SS) to achieve high-performance sensing. In this review, based on an analysis of the critical factors that are unfavorable for a steep SS in OFETs, the corresponding representative strategies for achieving steep SS are summarized, and the advantages and limitations of these strategies are comprehensively discussed. Furthermore, a bridge between SS and OFET sensor performance is established. Subsequently, the applications of OFETs with steep SS in sensor systems, including pressure sensors, photosensors, biochemical sensors, and electrophysiological signal sensors. Lastly, the challenges faced in developing OFET sensors with steep SS are discussed. This study provides insights into the design and application of high-performance OFET sensor systems.

FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design.

In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal-semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Sub-Boltzmann Switching, Hysteresis-Free Charge Modulated Negative Differential Resistance FinFET.

The ever-increasing power consumption in integrated circuits has raised concerns about the relentless doubling of transistor density in chips and cost drop per combinational/sequential circuits. To address the physical limit of thermionic emission carrier transport (i.e., subthreshold swing >60 mV/decade at 300 K), alternative charge-transport mechanisms or the implementation of functional substances have been attempted but without appreciable success. One such choice is to take advantage of negative differential resistance with the activation of localized electrons or migration of atom and oxygen vacancies to extend the capabilities of Si-transistors. However, inconsistency in current during forward/reverse bias sweep is confronted as a notable weak point. This work proposes an eye-catching solution to modulating potential distribution between a resistance switching layer and a transistor by employing charge trapping within a hafnium zirconium oxide layer. This approach introduces features advancing the potential of "More Moore" technologies.

WSe2 Negative Capacitance Field-Effect Transistor for Biosensing Applications.

Field-effect transistor (FET) biosensors based on two-dimensional (2D) materials are highly sought after for their high sensitivity, label-free detection, fast response, and ease of on-chip integration. However, the subthreshold swing (SS) of FETs is constrained by the Boltzmann limit and cannot fall below 60 mV/dec, hindering sensor sensitivity enhancement. Additionally, the gate-leakage current of 2D material biosensors in liquid environments significantly increases, adversely affecting the detection accuracy and stability. Based on the principle of negative capacitance, this paper presents for the first time a two-dimensional material WSe2 negative capacitance field-effect transistor (NCFET) with a minimum subthreshold swing of 56 mV/dec in aqueous solution. The NCFET shows a significantly improved biosensor function. The pH detection sensitivity of the NCFET biosensor reaches 994 pH-1, nearly an order of magnitude higher than that of the traditional two-dimensional WSe2 FET biosensor. The Al2O3/HfZrO (HZO) bilayer dielectric in the NCFET not only contributes to negative capacitance characteristics in solution but also significantly reduces the leakage in solution. Utilizing an enzyme catalysis method, the WSe2 NCFET biosensor demonstrates a specific detection of glucose molecules, achieving a high sensitivity of 4800 A/A in a 5 mM glucose solution and a low detection limit (10-9 M). Further experiments also exhibit the ability of the biosensor to detect glucose in sweat.

Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power.

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

Reduced subthreshold swing in a vertical tunnel FET using a low-work-function live metal strip and a low-k material at the drain.

In this research paper, a vertical tunnel field-effect transistor (TFET) structure containing a live metal strip and a material with low dielectric constant is designed, and its performance metrics are analyzed in detail. Low-k SiO2 is incorporated in the channel-drain region. A live molybdenum metal strip with low work function is placed in a high-k HfO2 layer in the source-channel region. The device is examined by the parameters I off, subthreshold swing, threshold voltage, and I on/I off ratio. The introduction of a live metal strip in the dielectric layer closer to the source-channel interface results in a minimum subthreshold slope and a good I on/I off ratio. The low-k material at the drain reduces the gate-to-drain capacitance. Both the SiO2 layer and the live metal strip show excellent leakage current reduction to 1.4 × 10-17 A/µm. The design provides a subthreshold swing of 5 mV/decade, which is an excellent improvement in TFETs, an on-current of 1.00 × 10-5 A/µm, an I on/I off ratio of 7.14 × 1011, and a threshold voltage of 0.28 V.

Dual-Junction Field-Effect Transistor with Ultralow Subthreshold Swing Approaching the Theoretical Limit.

Metal-oxide-semiconductor field-effect transistors as basic electronic devices of integrated circuits have been greatly developed and widely used in the past decades. However, as the thickness of the conducting channel decreases, the interface electronic scattering between the gate oxide layer and the channel significantly impacts the performance of the transistor. To address this issue, van der Waals heterojunction field-effect transistors (vdWJFETs) have been proposed using two-dimensional semiconductors, which utilize the built-in electric field at the sharp van der Waals interface to regulate the channel conductance without the need of a complex gate oxide layer. In this study, a novel dual-junction vdWJFET composed of a MoS2 channel and a Te nanosheet gate has been developed. This device achieves an ultralow subthreshold swing (SS) and an extremely low current hysteresis, greatly surpassing the single-junction vdWJFET. In the transistor, the SS decreases from 475.04 to 68.3 mV dec-1, nearly approaching the theoretical limit of 60 mV dec-1 at room temperature. The pinch-off voltage (Vp) decreases from -4.5 to -0.75 V, with a current hysteresis of ∼10 mV and a considerable field-effect mobility (µ) of 36.43 cm2 V-1 s-1. The novel dual-junction vdWJFET provides a new approach to realize a transistor with a theoretical ideal SS and a negligible current hysteresis toward low-power electronic applications.

Overcoming the Unfavorable Effects of "Boltzmann Tyranny:" Ultra-Low Subthreshold Swing in Organic Phototransistors via One-Transistor-One-Memristor Architecture.

Organic phototransistors (OPTs), as photosensitive organic field-effect transistors (OFETs), have gained significant attention due to their pivotal roles in imaging, optical communication, and night vision. However, their performance is fundamentally limited by the Boltzmann distribution of charge carriers, which constrains the average subthreshold swing (SSave) to a minimum of 60 mV/decade at room temperature. In this study, an innovative one-transistor-one-memristor (1T1R) architecture is proposed to overcome the Boltzmann limit in conventional OFETs. By replacing the source electrode in an OFET with a memristor, the 1T1R device exploits the memristor's sharp resistance state transitions to achieve an ultra-low SSave of 18 mV/decade. Consequently, the 1T1R devices demonstrate remarkable sensitivity to photo illumination, with a high specific detectivity of 3.9 × 109 cm W-1Hz1/2, outperforming conventional OPTs (4.9 × 104 cm W-1Hz1/2) by more than four orders of magnitude. The 1T1R architecture presents a potentially universal solution for overcoming the detrimental effects of "Boltzmann tyranny," setting the stage for the development of ultra-low SSave devices in various optoelectronic applications.

Single-Gate MoS2 Tunnel FET with a Thickness-Modulated Homojunction.

Two-dimensional (2D) materials stand as a promising platform for tunnel field-effect transistors (TFETs) in the pursuit of low-power electronics for the Internet of Things era. This promise arises from their dangling bond-free van der Waals heterointerface. Nevertheless, the attainment of high device performance is markedly impeded by the requirement of precise control over the 2D assembly with multiple stacks of different layers. In this study, we addressed a thickness-modulated n/p+-homojunction prepared from Nb-doped p+-MoS2 crystal, where the issue on interface traps can be neglected without any external interface control due to the homojunction. Notably, our observations reveal the existence of a negative differential resistance, even at room temperature (RT). This signifies the successful realization of TFET operation under type III band alignment conditions by a single gate at RT, suggesting that the dominant current mechanism is band-to-band tunneling due to the ideal interface.

Ultrafast Negative Capacitance Transition for 2D Ferroelectric MoS2/Graphene Transistor.

Negative capacitance gives rise to subthreshold swing (SS) below the fundamental limit by efficient modulation of surface potential in transistors. While negative-capacitance transition is reported in polycrystalline Pb(Zr0.2Ti0.8)O3 (PZT) and HfZrO2 (HZO) thin-films in few microseconds timescale, low SS is not persistent over a wide range of drain current when used instead of conventional dielectrics. In this work, the clear nano-second negative transition states in 2D single-crystal CuInP2S6 (CIPS) flakes have been demonstrated by an alternative fast-transient measurement technique. Further, integrating this ultrafast NC transition with the localized density of states of Dirac contacts and controlled charge transfer in the CIPS/channel (MoS2/graphene) a state-of-the-art device architecture, negative capacitance Dirac source drain field effect transistor (FET) is introduced. This yields an ultralow SS of 4.8 mV dec-1 with an average sub-10 SS across five decades with on-off ratio exceeding 107, by simultaneous improvement of transport and body factors in monolayer MoS2-based FET, outperforming all previous reports. This approach could pave the way to achieve ultralow-SS FETs for future high-speed and low-power electronics.

PZT-Enabled MoS2 Floating Gate Transistors: Overcoming Boltzmann Tyranny and Achieving Ultralow Energy Consumption for High-Accuracy Neuromorphic Computing.

Low-power electronic devices play a pivotal role in the burgeoning artificial intelligence era. The study of such devices encompasses low-subthreshold swing (SS) transistors and neuromorphic devices. However, conventional field-effect transistors (FETs) face the inherent limitation of the "Boltzmann tyranny", which restricts SS to 60 mV decade-1 at room temperature. Additionally, FET-based neuromorphic devices lack sufficient conductance states for highly accurate neuromorphic computing due to a narrow memory window. In this study, we propose a pioneering PZT-enabled MoS2 floating gate transistor (PFGT) configuration, demonstrating a low SS of 46 mV decade-1 and a wide memory window of 7.2 V in the dual-sweeping gate voltage range from -7 to 7 V. The wide memory window provides 112 distinct conductance states for PFGT. Moreover, the PFGT-based artificial neural network achieves an outstanding facial-recognition accuracy of 97.3%. This study lays the groundwork for the development of low-SS transistors and highly energy efficient artificial synapses utilizing two-dimensional materials.

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials.

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60 mV dec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state, and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket.

In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 [Formula: see text] 10-6 A/µm, and the ION/IOFF ratio is 1.34 [Formula: see text] 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf0.5Zr0.5O2 Thin Films.

The emergence of complementary metal-oxide semiconductor (CMOS)-compatible HfO2-based ferroelectric materials provides a promising way to achieve ferroelectric field-effect transistors (FeFETs) with a steep subthreshold swing (SS) reduced to below the Boltzmann thermodynamics limit (∼60 mV/dec at room temperature), which has important implications for lowering power consumption. In this work, a metal-oxide-semiconductor field-effect transistor (MOSFET) is connected with Hf0.5Zr0.5O2 (HZO)-based ferroelectric capacitors with different capacitances. By adjusting the capacitance of ferroelectric capacitors, an ultralow SS of ∼0.34 mV/dec in HfO2-based FeFETs can be achieved. More interestingly, by designing the sweeping voltage sequences, the SS can be adjusted to be 0 mV/dec with the drain current ranging over six orders of magnitude, and the threshold voltage for turning on the MOSFET can be further reduced. The manipulated SS could be attributed to the evolution of ferroelectric switching. Our work contributes to understanding the origin of ultralow SS in ferroelectric MOSFETs and the realization of low-power devices.

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors.

Boltzmann distribution thermal tails of carriers restrain the subthreshold swing (SS) of field-effect transistors (FETs) to be lower than 60 mV/decade at room temperature, which restrains the reduction of operate-voltage and power consumption of transistors. The negative-capacitance FET (NC FET) is expected to break through this physical limit and obtain a steep SS by amplifying the gate voltage through the negative capacitance effect of the ferroelectric thin film, providing a new way to further reduce the power consumption of the transistor at the end of Moore's law. Here, we show a MoS2 NC FET with a CuInP2S6 ferroelectric, exhibiting a large on/off ratio of 108, a steep SS as low as 6 mV/decade, and a wide sub-60 mV/decade drain current range of more than 4 orders of magnitude while sacrificially inducing a huge hysteresis larger than 500 mV. Furthermore, we found that by inserting the h-phase boron nitride (h-BN) layer with suitable thickness, the dielectric capacitance matches the ferroelectric negative capacitance better, and thus the hysteresis on the transfer curve is reduced, and the ideal switching-behavior transistors with SS as low as 62 mV/decade and only 5 mV negligible hysteresis were obtained. Our work demonstrates that under the capacitance-matching condition, the hysteresis-free negative-capacitance transistors do not act as the predicted steep-slope transistors, but their voltage-saving still occurs instead as a type of effective transconductance booster with more than 20 times transconductance amplification.

Bilateral sidewall engineering Si1-xGexiTFET for low power display application.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve theION, resulting in a lower subthreshold swing average (S.Savg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that theS.Savgis improved to 21.5 mV dec-1with anION/IOFFratio of 106 atVD= 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec-1has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation.

In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at VD = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SSavg) of 30.5 mV/dec, an Ion of 3.12 × 10-5 A/µm and an Ion/Ioff ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

Novel Mixed-Dimensional hBN-Passivated Silicon Nanowire Reconfigurable Field Effect Transistors: Fabrication and Characterization.

This work demonstrates the novel concept of a mixed-dimensional reconfigurable field effect transistor (RFET) by combining a one-dimensional (1D) channel material such as a silicon (Si) nanowire with a two-dimensional (2D) material as a gate dielectric. An RFET is an innovative device that can be dynamically programmed to perform as either an n- or p-FET by applying appropriate gate potentials. In this work, an insulating 2D material, hexagonal boron nitride (hBN), is introduced as a gate dielectric and encapsulation layer around the nanowire in place of a thermally grown or atomic-layer-deposited oxide. hBN flake was mechanically exfoliated and transferred onto a silicon nanowire-based RFET device using the dry viscoelastic stamping transfer technique. The thickness of the hBN flakes was investigated by atomic force microscopy and transmission electron microscopy. The ambipolar transfer characteristics of the Si-hBN RFETs with different gating architectures showed a significant improvement in the device's electrical parameters due to the encapsulation and passivation of the nanowire with the hBN flake. Both n- and p-type characteristics measured through the top gate exhibited a reduction of hysteresis by 10-20 V and an increase in the on-off ratio (ION/IOFF) by 1 order of magnitude (up to 108) compared to the values measured for unpassivated nanowire. Specifically, the hBN encapsulation provided improved electrostatic top gate coupling, which is reflected in the enhanced subthreshold swing values of the devices. For a single nanowire, an improvement up to 0.97 and 0.5 V/dec in the n- and p-conduction, respectively, is observed. Due to their dynamic switching and polarity control, RFETs boast great potential in reducing the device count, lowering power consumption, and playing a crucial role in advanced electronic circuitry. The concept of mixed-dimensional RFET could further strengthen its functionality, opening up new pathways for future electronics.