Digital implementation of hierarchical vector quantization.
IEEE Trans Neural Netw
; 14(5): 1072-84, 2003.
Article
em En
| MEDLINE
| ID: mdl-18244561
ABSTRACT
A formal methodology drives the design and realization of a digital very large-scale integration (VLSI) device supporting hierarchical vector quantization (HVQ) in computation-intensive coding applications. The hardware-oriented model-selection approach enhances the Minimum Description Length criterion with circuit-related aspects that allow consistent and efficient design. The resulting model parameters drive the subsequent realization in digital circuitry, which has first been implemented in field-programmable gate array (FPGA) technology to verify its correctness. The eventual VLSI realization results in an HVQ chip providing cost-effective, computationally efficient real-time performances. Real-world applications support the consistency of the vector quantization approach and the effectiveness of the HVQ device.
Texto completo:
1
Coleções:
01-internacional
Base de dados:
MEDLINE
Tipo de estudo:
Prognostic_studies
Idioma:
En
Revista:
IEEE Trans Neural Netw
Ano de publicação:
2003
Tipo de documento:
Article