III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Electrical properties of GaSb/InAsSb core/shell nanowires.

Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2-3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires. Maximum intrinsic field effect mobilities of 200 and 42 cm(2) Vs(-1) were extracted for the GaSb/InAsSb core/shell and bare-GaSb NWs at room temperature, respectively. The temperature-dependence of the mobility suggests that ionized impurity scattering is the dominant scattering mechanism in bare GaSb while phonon scattering dominates in core/shell nanowires. Top-gated field effect transistors were fabricated based on radial GaSb/InAsSb heterostructure nanowires with shell thicknesses in the range 5-7 nm. The fabricated devices exhibited ambipolar conduction, where the output current was studied as a function of AC gate voltage and frequency. Frequency doubling was experimentally demonstrated up to 20 kHz. The maximum operating frequency was limited by parasitic capacitance associated with the measurement chip geometry.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

Single InAs/GaSb nanowire low-power CMOS inverter.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Effects of crystal phase mixing on the electrical properties of InAs nanowires.

We report a systematic study of the relationship between crystal quality and electrical properties of InAs nanowires grown by MOVPE and MBE, with crystal structure varying from wurtzite to zinc blende. We find that mixtures of these phases can exhibit up to 2 orders of magnitude higher resistivity than single-phase nanowires, with a temperature-activated transport mechanism. However, it is also found that defects in the form of stacking faults and twin planes do not significantly affect the resistivity. These findings are important for nanowire-based devices, where uncontrolled formation of particular polytype mixtures may lead to unacceptable device variability.

High current density Esaki tunnel diodes based on GaSb-InAsSb heterostructure nanowires.

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.

Self-seeded, position-controlled InAs nanowire growth on Si: A growth parameter study.

In this work, the nucleation and growth of InAs nanowires on patterned SiO(2)/Si(111) substrates is studied. It is found that the nanowire yield is strongly dependent on the size of the etched holes in the SiO(2), where openings smaller than 180 nm lead to a substantial decrease in nucleation yield, while openings larger than ≈500nm promote nucleation of crystallites rather than nanowires. We propose that this is a result of indium particle formation prior to nanowire growth, where the size of the indium particles, under constant growth parameters, is strongly influenced by the size of the openings in the SiO(2) film. Nanowires overgrowing the etched holes, eventually leading to a merging of neighboring nanowires, shed light into the growth mechanism.

Growth mechanism of self-catalyzed group III-V nanowires.

Group III-V nanowires offer the exciting possibility of epitaxial growth on a wide variety of substrates, most importantly silicon. To ensure compatibility with Si technology, catalyst-free growth schemes are of particular relevance, to avoid impurities from the catalysts. While this type of growth is well-documented and some aspects are described, no detailed understanding of the nucleation and the growth mechanism has been developed. By combining a series of growth experiments using metal-organic vapor phase epitaxy, as well as detailed in situ surface imaging and spectroscopy, we gain deeper insight into nucleation and growth of self-seeded III-V nanowires. By this mechanism most work available in literature concerning this field can be described.