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Barium titanate-on-insulator has demonstrated excellent vertical optical confinement, low loss, and strong electro-optic properties. To fabricate a waveguide-based device, a region of higher refractive index must be created to confine a propagating mode, one way of which is through dry etching to form a ridge. However, despite recent progress achieved in etching barium titanate and similar materials, the sidewall and surface roughness resulting from the physical etching typically used limit the achievable ridge depth. This motivates the exploration of etch-free methods to achieve the required index contrast. Here, we introduce three etch-free methods to create a refractive index contrast in barium titanate-on-insulator, including a metal diffusion method, proton beam irradiation method, and crystallinity control method. Notably, molybdenum-diffused barium titanate leads to a large index change of up to 0.17. The methods provided in this work can be further developed to fabricate various on-chip barium titanate optical waveguide-based devices.
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By harnessing the physically unclonable properties, true random number generators (TRNGs) offer significant promises to alleviate security concerns by generating random bitstreams that are cryptographically secured. However, fundamental challenges remain as conventional hardware often requires complex circuitry design, showing a predictable pattern that is susceptible to machine learning attacks. Here, a low-power self-corrected TRNG is presented by exploiting the stochastic ferroelectric switching and charge trapping in molybdenum disulfide (MoS2 ) ferroelectric field-effect transistors (Fe-FET) based on hafnium oxide complex. The proposed TRNG exhibits enhanced stochastic variability with near-ideal entropy of ≈1.0, Hamming distance of ≈50%, independent autocorrelation function, and reliable endurance cycle against temperature variations. Furthermore, its unpredictable feature is systematically examined by machine learning attacks, namely the predictive regression model and the long-short-term-memory (LSTM) approach, where nondeterministic predictions can be concluded. Moreover, the generated cryptographic keys from the circuitry successfully pass the National Institute of Standards and Technology (NIST) 800-20 statistical test suite. The potential of integrating ferroelectric and 2D materials is highlighted for advanced data encryption, offering a novel alternative to generate truly random numbers.
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Spintronics has been recently extended to neuromorphic computing because of its energy efficiency and scalability. However, a biorealistic spintronic neuron with probabilistic "spiking" and a spontaneous reset functionality has not been demonstrated yet. Here, we propose a biorealistic spintronic neuron device based on the heavy metal (HM)/ferromagnet (FM)/antiferromagnet (AFM) spin-orbit torque (SOT) heterostructure. The spintronic neuron can autoreset itself after firing due to the exchange bias of the AFM. The firing process is inherently stochastic because of the competition between the SOT and AFM pinning effects. We also implement a restricted Boltzmann machine (RBM) and stochastic integration multilayer perceptron (SI-MLP) using our proposed neuron. Despite the bit-width limitation, the proposed spintronic model can achieve an accuracy of 97.38% in pattern recognition, which is even higher than the baseline accuracy (96.47%). Our results offer a spintronic device solution to emulate biologically realistic spiking neurons.
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Modelos Neurológicos , Neurônios , Neurônios/fisiologia , Redes Neurais de Computação , Imãs , TorqueRESUMO
The growth of artificial intelligence leads to a computational burden in solving non-deterministic polynomial-time (NP)-hard problems. The Ising computer, which aims to solve NP-hard problems faces challenges such as high power consumption and limited scalability. Here, we experimentally present an Ising annealing computer based on 80 superparamagnetic tunnel junctions (SMTJs) with all-to-all connections, which solves a 70-city traveling salesman problem (TSP, 4761-node Ising problem). By taking advantage of the intrinsic randomness of SMTJs, implementing global annealing scheme, and using efficient algorithm, our SMTJ-based Ising annealer outperforms other Ising schemes in terms of power consumption and energy efficiency. Additionally, our approach provides a promising way to solve complex problems with limited hardware resources. Moreover, we propose a cross-bar array architecture for scalable integration using conventional magnetic random-access memories. Our results demonstrate that the SMTJ-based Ising computer with high energy efficiency, speed, and scalability is a strong candidate for future unconventional computing schemes.
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Spintronics-based artificial neural networks (ANNs) exhibiting nonvolatile, fast, and energy-efficient computing capabilities are promising neuromorphic hardware for performing complex cognitive tasks of artificial intelligence and machine learning. Early experimental efforts focused on multistate device concepts to enhance synaptic weight precisions, albeit compromising on cognitive accuracy due to their low magnetoresistance. Here, we propose a hybrid approach based on the tuning of tunnel magnetoresistance (TMR) and the number of states in the compound magnetic tunnel junctions (MTJs) to improve the cognitive performance of an all-spin ANN. A TMR variation of 33-78% is controlled by the free layer (FL) thickness wedge (1.6-2.6 nm) across the wafer. Meanwhile, the number of resistance states in the compound MTJ is manipulated by varying the number of constituent MTJ cells (n = 1-3), generating n + 1 states with a TMR difference between consecutive states of at least 21%. Using MNIST handwritten digit and fashion object databases, the test accuracy of the compound MTJ ANN is observed to increase with the number of intermediate states for a fixed FL thickness or TMR. Meanwhile, the test accuracy for a 1-cell MTJ increases linearly by 8.3% and 7.4% for handwritten digits and fashion objects, respectively, with increasing TMR. Interestingly, a multifarious TMR dependence of test accuracy is observed with the increasing synaptic complexity in the 2- and 3-cell MTJs. By leveraging on the bimodal tuning of multilevel and TMR, we establish viable paths for enhancing the cognitive performance of spintronic ANN for in-memory and neuromorphic computing.
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The quest to mimic the multistate synapses for bioinspired computing has triggered nascent research that leverages the well-established magnetic tunnel junction (MTJ) technology. Early works on the spin transfer torque MTJ-based artificial neural network (ANN) are susceptible to poor thermal reliability, high latency, and high critical current densities. Meanwhile, work on spin-orbit torque (SOT) MTJ-based ANN mainly utilized domain wall motion, which yields negligibly small readout signals differentiating consecutive states and has designs that are incompatible with technological scale-up. Here, we propose a multistate device concept built upon a compound MTJ consisting of multiple SOT-MTJs (number of MTJs, n = 1-4) on a shared write channel, mimicking the spin-based ANN. The n + 1 resistance states representing varying synaptic weights can be tuned by varying the voltage pulses (±1.5-1.8 V), pulse duration (100-300 ns), and applied in-plane fields (5.5-10.5 mT). A large TMR difference of more than 13.6% is observed between two consecutive states for the 4-cell compound MTJ, a 4-fold improvement from reported state-of-the-art spin-based synaptic devices. The ANN built upon the compound MTJ shows high learning accuracy for digital recognition tasks with incremental states and retraining, achieving test accuracy as high as 95.75% in the 4-cell compound MTJ. These results provide an industry-compatible platform to integrate these multistate SOT-MTJ synapses directly into neuromorphic architecture for in-memory and unconventional computing applications.
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Simulated annealing (SA) attracts more attention among classical heuristic algorithms because many combinatorial optimization problems can be easily recast as the ground state search problem of the Ising Hamiltonian. However, for practical implementation, the annealing process cannot be arbitrarily slow and hence, it may deviate from the expected stationary Boltzmann distribution and become trapped in a local energy minimum. To overcome this problem, this paper proposes a heuristic search algorithm by expanding search space from a Markov chain to a recursive depth limited tree based on SA, where the parent and child nodes represent the current and future spin states. At each iteration, the algorithm selects the best near-optimal solution within the feasible search space by exploring along the tree in the sense of "look ahead". Furthermore, motivated by the coherent Ising machine (CIM), the discrete representation of spin states is relaxed to a continuous representation with a regularization term, which enables the use of the reduced dynamics of the oscillators to explore the surrounding neighborhood of the selected tree nodes. We tested our algorithm on a representative NP-hard problem (MAX-CUT) to illustrate the effectiveness of the proposed algorithm compared to semi-definite programming (SDP), SA, and simulated CIM. Our results show that with the primal heuristics SA and CIM, our high-level tree search strategy is able to provide solutions within fewer epochs for Ising formulated combinatorial optimization problems.
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Memristor crossbar with programmable conductance could overcome the energy consumption and speed limitations of neural networks when executing core computing tasks in image processing. However, the implementation of crossbar array (CBA) based on ultrathin 2D materials is hindered by challenges associated with large-scale material synthesis and device integration. Here, a memristor CBA is demonstrated using wafer-scale (2-inch) polycrystalline hafnium diselenide (HfSe2 ) grown by molecular beam epitaxy, and a metal-assisted van der Waals transfer technique. The memristor exhibits small switching voltage (0.6 V), low switching energy (0.82 pJ), and simultaneously achieves emulation of synaptic weight plasticity. Furthermore, the CBA enables artificial neural network with a high recognition accuracy of 93.34%. Hardware multiply-and-accumulate (MAC) operation with a narrow error distribution of 0.29% is also demonstrated, and a high power efficiency of greater than 8-trillion operations per second per Watt is achieved. Based on the MAC results, hardware convolution image processing can be performed using programmable kernels (i.e., soft, horizontal, and vertical edge enhancement), which constitutes a vital function for neural network hardware.
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Háfnio , Redes Neurais de Computação , Computadores , Fenômenos FísicosRESUMO
Two-terminal resistive switching devices are commonly plagued with longstanding scientific issues including interdevice variability and sneak current that lead to computational errors and high-power consumption. This necessitates the integration of a separate selector in a one-transistor-one-RRAM (1T-1R) configuration to mitigate crosstalk issue, which compromises circuit footprint. Here, we demonstrate a multi-terminal memtransistor crossbar array with increased parallelism in programming via independent gate control, which allows in situ computation at a dense cell size of 3-4.5 F2 and a minimal sneak current of 0.1 nA. Moreover, a low switching energy of 20 fJ/bit is achieved at a voltage of merely 0.42 V. The architecture is capable of performing multiply-and-accumulate operation, a core computing task for pattern classification. A high MNIST recognition accuracy of 96.87% is simulated owing to the linear synaptic plasticity. Such computing paradigm is deemed revolutionary toward enabling data-centric applications in artificial intelligence and Internet-of-things.
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Recently, a great deal of scientific endeavour has been devoted to developing spin-based neuromorphic platforms owing to the ultra-low-power benefits offered by spin devices and the inherent correspondence between spintronic phenomena and the desired neuronal, synaptic behavior. While domain wall motion-based threshold activation unit has previously been demonstrated for neuromorphic circuits, it remains well known that neurons with threshold activation cannot completely learn nonlinearly separable functions. This paper addresses this fundamental limitation by proposing a novel domain wall motion-based dual-threshold activation unit with additional nonlinearity in its function. Furthermore, a new learning algorithm is formulated for a neuron with this activation function. We perform 100 trials of tenfold training and testing of our neural networks on real-world datasets taken from the UCI machine learning repository. On an average, the proposed algorithm achieves [Formula: see text] lower misclassification rate (MCR) than the traditional perceptron learning algorithm. In a circuit-level simulation, the neural networks with the proposed activation unit are observed to outperform the perceptron networks by as much as [Formula: see text] MCR. The energy consumption of a neuron having the proposed domain wall motion-based activation unit averages to [Formula: see text] approximately.
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Modelos Neurológicos , Redes Neurais de Computação , Algoritmos , Bases de Dados Factuais , Desenho de Equipamento , Humanos , Neurônios/fisiologiaRESUMO
Nanoelectronic devices with specifically designed structures for performance promotion or function expansion are of great interest, aiming for diversified advanced nanoelectronic systems. In this work, we report a dual-material gate (DMG) carbon nanotube (CNT) device with multiple functions, which can be configured either as a high-performance p-type field-effect transistor (FET) or a diode by changing the input manners of the device. When operating as a FET, the device exhibits a large current on/off ratio of more than 108 and a drain-induced barrier lowering of 97.3 mV V-1. When configured as a diode, the rectification ratio of the device can be greater than 105. We then demonstrate configurable analog and digital integrated circuits that are enabled by utilizing these devices. The configurability enables the realization of transformable functions in a single device or circuits, which gives future electronic systems the flexibility to adapt to the diverse requirements of their applications and/or ever-changing operating environments.