One-Stop Strategy for Obtaining Controllable Sensitivity and Feasible Self-Patterning in Silver Nanowires/Elastomer Nanocomposite-Based Stretchable Ultrathin Strain Sensors.

In this study, selective photo-oxidation (SPO) is proposed as a simple, fast, and scalable one-stop strategy that enables simultaneous self-patterning and sensitivity adjustment of ultrathin stretchable strain sensors. The SPO of an elastic substrate through irradiation time-controlled ultraviolet treatment in a confined region enables precise tuning of both the surface energy and the elastic modulus. SPO induces the hydrophilization of the substrate, thereby allowing the self-patterning of silver nanowires (AgNWs). In addition, it promotes the formation of nonpermanent microcracks of AgNWs/elastomer nanocomposites under the action of strain by increasing the elastic modulus. This effect improves sensor sensitivity by suppressing the charge transport pathway. Consequently, AgNWs are directly patterned with a width of 100 µm or less on the elastic substrate, and AgNWs/elastomer-based ultrathin and stretchable strain sensors with controlled sensitivity work reliably in various operating frequencies and cyclic stretching. Sensitivity-controlled strain sensors successfully detect both small and large movements of the human hand.

Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time.

We present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a Si/SiGe heterojunction double-gate MOSFET. In the proposed 1T-DRAM, the program process is based on band-to-band tunneling (BTBT) between gate 1 and gate 2 regions, and a sensing margin is defined by the amount of excess holes stored in the SiGe body region. Therefore, the sensing margin and retention time were affected by SiGe in the body region. The BTBT rate, enhanced by the small band-gap energy in SiGe, increased the sensing margin. The Si/SiGe heterojunction between the source/drain and body regions formed a potential barrier for hole carriers. The retention time was improved by suppressing the diffusion of hole carriers in the floating-body storage node. In addition, the retention characteristic was also enhanced by applying a gate underlap structure, which significantly reduced the electric field-induced recombination rate. The optimized device with a Si0.7Ge0.3 body and underlap length (Lunderlap) of 5 nm exhibited a high sensing margin of 6.16 µA/µm and long retention time of 131 ms at a high temperature of 358 K.

Design Optimization and Analysis of InGaAs/InAs/InGaAs Heterojunction-Based Electron Hole Bilayer Tunneling FETs.

In this study, we have designed and analyzed the electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) based on various III-V compound semiconductor materials using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET has lower subthreshold swing (S) and higher on-state current (Ion) than the conventional planar TFET, using band-to-band tunneling (BTBT) across the source-to-channel junction. It uses a bias-induced BTBT across the EHB formed by an electric field between the two gates. The III-V compound semiconductors have been applied to the EHB TFETs to improve the switching performances and current drivability owing to their superior material properties such as high electron mobility and high tunneling probability. After the design and analysis of devices based on various compound semiconductors, in terms of primary DC characteristics, a lower bandgap material (InAs) has been inserted in the tunneling region of the In0.53Ga0.47As EHB TFET to enhance the tunneling rate. This paper proposes an EHB TFET that uses vertically stacked InGaAs/InAs/InGaAs layers. Moreover, the design optimization process has been performed via simulations. The simulation results of the proposed EHB TFET show remarkable performances with Ion of 739.6 µA/µm, S of 1.9 mV/dec, and threshold voltage (Vth) of 7 mV at VDS 0.5 V.

Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor.

In this work, an InGaAs/GaAsSb-based P-type gate-all-around (GAA) arch-shaped tunneling fieldeffect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. The device performance was investigated in views of the on-state current (Ion), subthreshold swing (SS), and Ion/Ioff ratio. For high current drivability, InGaAs/GaAsSb heterojunction is used to form the broken bandgap. Owing to the GAA arch-shaped structure of the TFET, the tunneling region between source and channel extended, thus Ion and SS are improved. However, it has some performance variations that are related with the height of the source region (Hsource), the epitaxially grown thickness of the channel (tepi), and the height of the drain region (Hdrain). Therefore, we performed a design optimization of the proposed device with the variables of Hsource, tepi, and Hdrain. The designed and optimized InGaAs/GaAsSb-based P-type GAA arch-shaped TFET demonstrated an Ion of 215 µA/µm SS of 18 mV/dec and Ion/Ioff of 1.64 × 1012.

Analysis of Electrical Characteristics of InAlGaN/GaN-Based High Electron Mobility Transistors with AlGaN Back Barriers.

In this study, the effect of an AlGaN back-barrier on the electrical characteristics of InAlGaN/GaN high electron mobility transistors (HEMTs) was investigated. The dependence of the thickness and the Al composition of the AlGaN back-barrier on the off-state current (Ioff) of the devices was investigated. An InAlGaN/GaN HEMT with an Al0.1GaN back-barrier of thickness 20 nm exhibited lower Ioff because of the carrier confinement effect, which was caused by the back-barrier. The carrier confinement effect also improved the maximum output current density and the transconductance (gm). Thus, the obtained cut-off frequency (fT) and maximum oscillation frequency (fmax) values for the InAlGaN/GaN HEMT with the 20 nm thick AlGaN back-barrier were 2.6% and 13% higher than those without the AlGaN back-barrier. In addition, the impact of the buffer trap density and GaN channel thickness were evaluated. In the case of a thickness of 20 nm for the Al0.1GaN back-barrier, a low Ioff was maintained although the trap density in the buffer layer was changed. In addition, as the gate length (LGa) decreased to 50 nm, the InAlGaN/GaN HEMT with the 20 nm thick Al0.1GaN back-barrier achieved better Ioff characteristics, lower drain-induced barrier lowering (DIBL) of 85.8 mV/V, and subthreshold swing (S) of 269 mV/dec owing to a reduction in the short-channel effect.

Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs.

This paper report a junctionless fin-type field-effect-transistor based capacitorless dynamic random access memory using three-dimensional technology computer-aided design simulations. The proposed 1T-DRAM is made up of a silicon germanium storage region surrounding a silicon fin. When the two materials form a heterojunction, a potential well is formed by the band discontinuity which carriers can be stored. During the program operation, band-to-band tunneling and gate-induced drain leakage occur simultaneously due to the gate and drain bias. Because of these phenomena, the electron-hole pair occurs, and generated holes are stored in the storage region by potential well. The holes formed are positively charged within the storage region, which mitigates the depletion of the channel and improves the operating current. The proposed device realizes the memory operation by the difference of the operating current depending on the presence or absence of the stored holes. In this work, the device is analyzed and optimized in detail. The proposed 1T-DRAM shows excellent performance with a retention time of 161 ms based on 50% of the maximum data margin.

Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET).

The Ge/GaAs-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) have been designed and optimized using technology computer-aided design (TCAD) simulations. In our previous work, the silicon-based A-TFET was designed and demonstrated. However, to progress the electrical characteristics of A-TFET, the III-V compound heterojunction structures which has enhanced electrical properties must be adopted. Thus, the germanium with gallium arsenide (Ge/GaAs) is considered as key materials of A-TFET. The proposed device has a Ge-based p-doped source, GaAs-based i-doped channel and GaAs-based n-doped drain. Due to the critical issues of device performances, the doping concentration of source and channel region (Dsource, Dchannel), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of Ge/GaAs-based GAA A-TFET. The DC characteristics such as on-state current (ion), off-state current (ioff), subthreshold-swing (S) were of extracted and analyzed. Finally, the proposed device has a gate length (LG) of 90 nm, Dsource 5 × 1019 cm-3, Dchannel of 1018 cm-3, tepi of 4 nm, Hsource of 90 nm, R of 10 nm and demonstrate an ion of 2 mA/µm, S of 12.9 mV/dec.

Simulation of One-Transistor Dynamic Random-Access Memory Based on Symmetric Double-Gate Si Junctionless Transistor.

In this study, one-transistor dynamic random-access memory (1T-DRAM) based on a symmetric double-gate Si junctionless transistor is proposed using technology computer-aided design simulation. The proposed device uses double gates that play different roles in realizing 1T-DRAM operation. Gate 1 is used as a switching node, and Gate 2 is used as a storage node. By controlling the different two gate workfunctions, a potential barrier is adjusted to store hole effectively. The operation characteristics were investigated regarding four different memory operation states to write "1", write "0", read, and hold. Also, the effects of two different gate workfunctions on sensing margin and retention characteristics are closely investigated. Through a set of optimally set gate workfunctions, 33 µA/µm of sensing margin and 38 ms of retention time have been obtained.

Nonlinear Transport in Organic Thin Film Transistors with Soluble Small Molecule Semiconductor.

Nonlinear transport is intensively explained through Poole-Frenkel (PF) transport mechanism in organic thin film transistors with solution-processed small molecules, which is, 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene. We outline a detailed electrical study that identifies the source to drain field dependent mobility. Devices with diverse channel lengths enable the extensive exhibition of field dependent mobility due to thermal activation of carriers among traps.

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing.

In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 µA/µm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed.

Formation of Cluster-Structured Metallic Filaments in Organic Memristors for Wearable Neuromorphic Systems with Bio-Mimetic Synaptic Weight Distributions.

With increasing demand for wearable electronics capable of computing huge data, flexible neuromorphic systems mimicking brain functions have been receiving much attention. Despite considerable efforts in developing practical neural networks utilizing several types of flexible artificial synapses, it is still challenging to develop wearable systems for complex computations due to the difficulties in emulating continuous memory states in a synaptic component. In this study, polymer conductivity is analyzed as a crucial factor in determining the growth dynamics of metallic filaments in organic memristors. Moreover, flexible memristors with bio-mimetic synaptic functions such as linearly tunable weights are demonstrated by engineering the polymer conductivity. In the organic memristor, the cluster-structured filaments are grown within the polymer medium in response to electric stimuli, resulting in gradual resistive switching and stable synaptic plasticity. Additionally, the device exhibits the continuous and numerous non-volatile memory states due to its low leakage current. Furthermore, complex hardware neural networks including ternary logic operators and a noisy image recognitions system are successfully implemented utilizing the developed memristor arrays. This promising concept of creating flexible neural networks with bio-mimetic weight distributions will contribute to the development of a new computing architecture for energy-efficient wearable smart electronics.

Effect of Electrochemically Active Top Electrode Materials on Nanoionic Conductive Bridge Y2O3 Random-Access Memory.

Herein, sol-gel-processed Y2O3 resistive random-access memory (RRAM) devices were fabricated. The top electrodes (TEs), such as Ag or Cu, affect the electrical characteristics of the Y2O3 RRAM devices. The oxidation process, mobile ion migration speed, and reduction process all impact the conductive filament formation of the indium-tin-oxide (ITO)/Y2O3/Ag and ITO/Y2O3/Cu RRAM devices. Between Ag and Cu, Cu can easily be oxidized due to its standard redox potential values. However, the conductive filament is easily formed using Ag TEs. After triggering the oxidation process, the formed Ag mobile metal ions can migrate faster inside Y2O3 active channel materials when compared to the formed Cu mobile metal ions. The fast migration inside the Y2O3 active channel materials successfully reduces the SET voltage and improves the number of programming-erasing cycles, i.e., endurance, which is one of the nonvolatile memory parameters. These results elucidate the importance of the electrochemical properties of TEs, providing a deeper understanding of how these factors influence the resistive switching characteristics of metal oxide-based atomic switches and conductive-metal-bridge-filament-based cells.

UV/Ozone-Treated and Sol-Gel-Processed Y2O3 Insulators Prepared Using Gelation-Delaying Precursors.

In this study, a Y2O3 insulator was fabricated via the sol-gel process and the effect of precursors and annealing processes on its electrical performance was studied. Yttrium(III) acetate hydrate, yttrium(III) nitrate tetrahydrate, yttrium isopropoxide oxide, and yttrium(III) tris (isopropoxide) were used as precursors, and UV/ozone treatment and high-temperature annealing were performed to obtain Y2O3 films from the precursors. The structure and surface morphologies of the films were characterized via grazing-incidence X-ray diffraction and scanning probe microscopy. Chemical component analysis was performed via X-ray spectroscopy. Electrical insulator characteristics were analyzed based on current density versus electrical field data and frequency-dependent dielectric constants. The Y2O3 films fabricated using the acetate precursor and subjected to the UV/ozone treatment showed a uniform and flat surface morphology with the lowest number of oxygen vacancy defects and unwanted byproducts. The corresponding fabricated capacitors showed the lowest current density (Jg) value of 10-8 A/cm2 at 1 MV/cm and a stable dielectric constant in a frequency range of 20 Hz-100 KHz. At 20 Hz, the dielectric constant was 12.28, which decreased to 10.5 at 105 Hz. The results indicate that high-quality, high-k insulators can be fabricated for flexible electronics using suitable precursors and the suggested low-temperature fabrication methods.

Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors.

The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications.

Analysis on RF parameters of nanoscale tunneling field-effect transistor based on InAs/InGaAs/InP heterojunctions.

Tunneling field-effect transistors (TFETs) based on the quantum mechanical band-to-band tunneling (BTBT) have advantages such as low off-current and subthreshold swing (S) below 60 mV/dec at room temperature. For these reasons, TFETs are considered as promising devices for low standby power (LSTP) applications. On the other hand, silicon (Si)-based TFETs have a drawback in low on-state current (lon) drivability. In this work, we suggest a gate-all-around (GAA) TFET based on compound semiconductors to improve device performances. The proposed device materials consist of InAs (source), InGaAs (channel), and InP (drain). According to the composition (x) of Ga in In1-xGa(x)As layer of the channel region, simulated devices have been investigated in terms of both direct-current (DC) and RF parameters including tunneling rate, transconductance (g(m)), gate capacitance (Cg), intrinsic delay time (tau), cut-off frequency (fT) and maximum oscillation frequency (f(max)). In this study, the obtained maximum values of tau, fT, and f(max) for GAA InAs/In0.9Ga0.1As/InP heterojunction TFET were 21.2 fs, 7 THz, and 18 THz, respectively.

Organic Memristor-Based Flexible Neural Networks with Bio-Realistic Synaptic Plasticity for Complex Combinatorial Optimization.

Hardware neural networks with mechanical flexibility are promising next-generation computing systems for smart wearable electronics. Several studies have been conducted on flexible neural networks for practical applications; however, developing systems with complete synaptic plasticity for combinatorial optimization remains challenging. In this study, the metal-ion injection density is explored as a diffusive parameter of the conductive filament in organic memristors. Additionally, a flexible artificial synapse with bio-realistic synaptic plasticity is developed using organic memristors that have systematically engineered metal-ion injections, for the first time. In the proposed artificial synapse, short-term plasticity (STP), long-term plasticity, and homeostatic plasticity are independently achieved and are analogous to their biological counterparts. The time windows of the STP and homeostatic plasticity are controlled by the ion-injection density and electric-signal conditions, respectively. Moreover, stable capabilities for complex combinatorial optimization in the developed synapse arrays are demonstrated under spike-dependent operations. This effective concept for realizing flexible neuromorphic systems for complex combinatorial optimization is an essential building block for achieving a new paradigm of wearable smart electronics associated with artificial intelligent systems.

Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc-Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment.

In this study, we used a low-pressure thermal annealing (LPTA) treatment to improve the switching characteristics and bias stability of zinc-tin oxide (ZTO) thin film transistors (TFTs). For this, we first fabricated the TFT and then applied the LPTA treatment at temperatures of 80 °C and 140 °C. The LPTA treatment reduced the number of defects in the bulk and interface of the ZTO TFTs. In addition, the changes in the water contact angle on the ZTO TFT surface indicated that the LPTA treatment reduced the surface defects. Hydrophobicity suppressed the off-current and instability under negative bias stress because of the limited absorption of moisture on the oxide surface. Moreover, the ratio of metal-oxygen bonds increased, while the ratio of oxygen-hydrogen bonds decreased. The reduced action of hydrogen as a shallow donor induced improvements in the on/off ratio (from 5.5 × 103 to 1.1 × 107) and subthreshold swing (8.63 to V·dec-1 and 0.73 V·dec-1), producing ZTO TFTs with excellent switching characteristics. In addition, device-to-device uniformity was significantly improved because of the reduced defects in the LPTA-treated ZTO TFTs.

Sol-Gel-Processed Y2O3 Multilevel Resistive Random-Access Memory Cells for Neural Networks.

Yttrium oxide (Y2O3) resistive random-access memory (RRAM) devices were fabricated using the sol-gel process on indium tin oxide/glass substrates. These devices exhibited conventional bipolar RRAM characteristics without requiring a high-voltage forming process. The effect of current compliance on the Y2O3 RRAM devices was investigated, and the results revealed that the resistance values gradually decreased with increasing set current compliance values. By regulating these values, the formation of pure Ag conductive filament could be restricted. The dominant oxygen ion diffusion and migration within Y2O3 leads to the formation of oxygen vacancies and Ag metal-mixed conductive filaments between the two electrodes. The filament composition changes from pure Ag metal to Ag metal mixed with oxygen vacancies, which is crucial for realizing multilevel cell (MLC) switching. Consequently, intermediate resistance values were obtained, which were suitable for MLC switching. The fabricated Y2O3 RRAM devices could function as a MLC with a capacity of two bits in one cell, utilizing three low-resistance states and one common high-resistance state. The potential of the Y2O3 RRAM devices for neural networks was further explored through numerical simulations. Hardware neural networks based on the Y2O3 RRAM devices demonstrated effective digit image classification with a high accuracy rate of approximately 88%, comparable to the ideal software-based classification (~92%). This indicates that the proposed RRAM can be utilized as a memory component in practical neuromorphic systems.

Low-Temperature Enhancement-Mode Amorphous Oxide Thin-Film Transistors in Solution Process Using a Low-Pressure Annealing.

The interest in low processing temperature for printable transistors is rapidly increasing with the introduction of a new form factor in electronics and the growing importance of high throughput. This paper reports the fabrication of low-temperature-processable enhancement-mode amorphous oxide thin-film transistors (TFTs) using the solution process. A facile low-pressure annealing (LPA) method is proposed for the activation of indium oxide (InOx) semiconductors at a significantly low processing temperature of 200 °C. Thermal annealing at a pressure of about ~10 Torr induces effective condensation in InOx even at a low temperature. As a result, the fabricated LPA InOx TFTs not only functioned in enhancement mode but also exhibited outstanding switching characteristics with a high on/off current ratio of 4.91 × 109. Furthermore, the LPA InOx TFTs exhibit stable operation under bias stress compared to the control device due to the low concentration of hydroxyl defects.

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley-Read-Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.