Nanoironing van der Waals Heterostructures toward Electrically Controlled Quantum Dots.

Assembling two-dimensional van der Waals (vdW)-layered materials into heterostructures is an exciting development that sparked the discovery of rich correlated electronic phenomena. vdW heterostructures also offer possibilities for designer device applications in areas such as optoelectronics, valley- and spintronics, and quantum technology. However, realizing the full potential of these heterostructures requires interfaces with exceptionally low disorder which is challenging to engineer. Here, we show that thermal scanning probes can be used to create pristine interfaces in vdW heterostructures. Our approach is compatible at both the material- and device levels, and monolayer WS2 transistors show up to an order of magnitude improvement in electrical performance from this technique. We also demonstrate vdW heterostructures with low interface disorder enabling the electrical formation and control of quantum dots that can be tuned from macroscopic current flow to the single-electron tunneling regime.

Liquid-Metal-Printed Ultrathin Oxides for Atomically Smooth 2D Material Heterostructures.

Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable high-k dielectrics that can achieve atomically smooth interfaces, small equivalent oxide thicknesses (EOTs), excellent gate control, and low leakage currents. Here, large-area liquid-metal-printed ultrathin Ga2O3 dielectrics for 2D electronics and optoelectronics are reported. The atomically smooth Ga2O3/WS2 interfaces enabled by the conformal nature of liquid metal printing are directly visualized. Atomic layer deposition compatibility with high-k Ga2O3/HfO2 top-gate dielectric stacks on a chemical-vapor-deposition-grown monolayer WS2 is demonstrated, achieving EOTs of ∼1 nm and subthreshold swings down to 84.9 mV/dec. Gate leakage currents are well within requirements for ultrascaled low-power logic circuits. These results show that liquid-metal-printed oxides can bridge a crucial gap in dielectric integration of 2D materials for next-generation nanoelectronics.