Percolating silicon nanowire networks with highly reproducible electrical properties.

Here, we report the morphological and electrical properties of self-assembled silicon nanowires networks, also called Si nanonets. At the macroscopic scale, the nanonets involve several millions of nanowires. So, the observed properties should result from large scale statistical averaging, minimizing thus the discrepancies that occur from one nanowire to another. Using a standard filtration procedure, the so-obtained Si nanonets are highly reproducible in terms of their morphology, with a Si nanowire density precisely controlled during the nanonet elaboration. In contrast to individual Si nanowires, the electrical properties of Si nanonets are highly consistent, as demonstrated here by the similar electrical properties obtained in hundreds of Si nanonet-based devices. The evolution of the Si nanonet conductance with Si nanowire density demonstrates that Si nanonets behave like standard percolating media despite the presence of numerous nanowire-nanowire intersecting junctions into the nanonets and the native oxide shell surrounding the Si nanowires. Moreover, when silicon oxidation is prevented or controlled, the electrical properties of Si nanonets are stable over many months. As a consequence, Si nanowire-based nanonets constitute a promising flexible material with stable and reproducible electrical properties at the macroscopic scale while being composed of nanoscale components, which confirms the Si nanonet potential for a wide range of applications including flexible electronic, sensing and photovoltaic applications.

Functional Devices from Bottom-Up Silicon Nanowires: A Review.

This paper summarizes some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting nanowires in functional devices, from single nanowires to large assemblies of nanowires such as nanonets (two-dimensional arrays of randomly oriented nanowires), are briefly reviewed. Subsequently, the main properties of nanowires are discussed followed by those of nanonets that benefit from the large numbers of nanowires involved. After describing the main techniques used for the growth of nanowires, in the context of functional device fabrication, the different techniques used for nanowire manipulation are largely presented as they constitute one of the first fundamental steps that allows the nanowire positioning necessary to start the integration process. The advantages and disadvantages of each of these manipulation techniques are discussed. Then, the main families of nanowire-based transistors are presented; their most common integration routes and the electrical performance of the resulting devices are also presented and compared in order to highlight the relevance of these different geometries. Because they can be bottlenecks, the key technological elements necessary for the integration of silicon nanowires are detailed: the sintering technique, the importance of surface and interface engineering, and the key role of silicidation for good device performance. Finally the main application areas for these silicon nanowire devices are reviewed.