Performance Limits and Advancements in Single 2D Transition Metal Dichalcogenide Transistor.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) allow for atomic-scale manipulation, challenging the conventional limitations of semiconductor materials. This capability may overcome the short-channel effect, sparking significant advancements in electronic devices that utilize 2D TMDs. Exploring the dimension and performance limits of transistors based on 2D TMDs has gained substantial importance. This review provides a comprehensive investigation into these limits of the single 2D-TMD transistor. It delves into the impacts of miniaturization, including the reduction of channel length, gate length, source/drain contact length, and dielectric thickness on transistor operation and performance. In addition, this review provides a detailed analysis of performance parameters such as source/drain contact resistance, subthreshold swing, hysteresis loop, carrier mobility, on/off ratio, and the development of p-type and single logic transistors. This review details the two logical expressions of the single 2D-TMD logic transistor, including current and voltage. It also emphasizes the role of 2D TMD-based transistors as memory devices, focusing on enhancing memory operation speed, endurance, data retention, and extinction ratio, as well as reducing energy consumption in memory devices functioning as artificial synapses. This review demonstrates the two calculating methods for dynamic energy consumption of 2D synaptic devices. This review not only summarizes the current state of the art in this field but also highlights potential future research directions and applications. It underscores the anticipated challenges, opportunities, and potential solutions in navigating the dimension and performance boundaries of 2D transistors.

Polarized Tunneling Transistor for Ultralow-Energy-Consumption Artificial Synapse toward Neuromorphic Computing.

Neural networks based on low-power artificial synapses can significantly reduce energy consumption, which is of great importance in today's era of artificial intelligence. Two-dimensional (2D) material-based floating-gate transistors (FGTs) have emerged as compelling candidates for simulating artificial synapses owing to their multilevel and nonvolatile data storage capabilities. However, the low erasing/programming speed of FGTs renders them unsuitable for low-energy-consumption artificial synapses, thereby limiting their potential in high-energy-efficient neuromorphic computing. Here, we introduce a FGT-inspired MoS2/Trap/PZT heterostructure-based polarized tunneling transistor (PTT) with a simple fabrication process and significantly enhanced erasing/programming speed. Distinct from the FGT, the PTT lacks a tunnel layer, leading to a marked improvement in its erasing/programming speed. The PTT's highest erasing/programming (operation) speed can reach ∼20 ns, which outperforms the performance of most FGTs based on 2D heterostructures. Furthermore, the PTT has been utilized as an artificial synapse, and its weight-update energy consumption can be as low as 0.0002 femtojoule (fJ), which benefits from the PTT's ultrahigh operation speed. Additionally, PTT-based artificial synapses have been employed in constructing artificial neural network simulations, achieving facial-recognition accuracy (95%). This groundbreaking work makes it possible for fabricating future high-energy-efficient neuromorphic transistors utilizing 2D materials.