A van der Waals Integrated Damage-Free Memristor Based on Layered 2D Hexagonal Boron Nitride.

2D materials with intriguing properties have been widely used in optoelectronics. However, electronic devices suffered from structural damage due to the ultrathin materials and uncontrolled defects at interfaces upon metallization, which hindered the development of reliable devices. Here, a damage-free Au/h-BN/Au memristor is reported using a clean, water-assisted metal transfer approach by physically assembling Au electrodes onto the layered h-BN which minimized the structural damage and undesired interfacial defects. The memristors demonstrate significantly improved performance with the coexistence of nonpolar and threshold switching as well as tunable current levels by controlling the compliance current, compared with devices with evaporated contacts. The devices integrated into an array show suppressed sneak path current and can work as both logic gates and latches to implement logic operations allowing in-memory computing. Cross-sectional scanning transmission electron microscopy analysis validates the feasibility of this nondestructive metal integration approach, the crucial role of high-quality atomically sharp interface in resistive switching, and a direct observation of percolation path. The underlying mechanism of boron vacancies-assisted transport is further supported experimentally by conductive atomic force microscopy free from process-induced damage, and theoretically by ab initio simulations.

Type-I Core-Shell ZnSe/ZnS Quantum Dot-Based Resistive Switching for Implementing Algorithm.

Core-shell semiconductor quantum dots (QDs) are one of the biggest nanotechnology successes so far. In particular, type-I QDs with straddling band offset possess the ability to enhance the charge carriers capturing which is useful for memory application. Here, the type-I core-shell QD-based bipolar resistive switching (RS) memory with anomalous multiple SET and RESET processes was demonstrated. The synergy and competition between space charge limited current conduction (arising from charge trapping in potential well of type-I QDs) and electrochemical metallization (ECM, originating from redox reaction of Ag electrode) process were employed for modulating the RS behavior. Through utilizing stochastic RS mechanisms in QD-based devices, four situations of RS behaviors can be classified into three states in Markov chain for implementing the application of a true random number generator. Furthermore, a 6 × 6 cross-bar array was demonstrated to realize the generation of random letters with case distinction.

The floating body effect of a WSe2 transistor with volatile memory performance.

The floating body effect in Meta-Stable-Dip RAM (MSDRAM) has been broadly employed in implementing single-transistor capacitor-less (1T0C) dynamic random access memory (DRAM) cells to break through the limitation of finite size reduction of peripheral capacitors. However, the majority of them were broadly demonstrated in conventional CMOS technology, while emerging semiconductor systems are rarely explored. Here, we creatively explore exfoliated multilayer tungsten diselenide (WSe2) for the application of 1T0C DRAM, breaking the limitation of channel thickness in the traditional architecture. Through the comparison of the electrical characteristics among three dual-gate transistors with different lengths of top-gate, we demonstrated the essential role of the floating body effect in achieving the function of 1T0C DRAM displaying two distinct states that are differentiated by hole population within the floating body. Moreover, according to the analysis of in situ electrostatic force microscopy (EFM) measurements and theoretical calculation via density functional theory (DFT), the injection of holes through band-to-band (B2B) tunneling can be ascribed to the effectively electrostatic modulation. These consequences prove our innovative concept to achieve the function of 1T0C DRAM through employing the ML WSe2, which is a vital step toward the breakthrough of the inherent limitations of DRAM cells.

A Perovskite Memristor with Large Dynamic Space for Analog-Encoded Image Recognition.

Reservoir computing (RC) is a computational architecture capable of efficiently processing temporal information, which allows low-cost hardware implementation. However, the previously reported memristor-based RC mostly utilized binarized data sets to reduce the difficulty of signal processing of the memristor, which inevitably induces data distortion to a certain extent, leading to poor network computing performance. Here, we report on a RC system in a fully memristive architecture based on solution-processed perovskite memristors. The perovskite memristor exhibits 10000 conductance states with a modulation range of more than 4 orders of magnitude. The obtained tens of thousands of finely spaced conductance states with a near-ideal analog property provide a sufficiently large dynamic range and enough intermediate states, which were further applied as a reservoir to map the feature information on different sequential inputs in an analog way. The computing capability of the image classification task of a Fashion-MNIST data set with a high recognition accuracy of up to 90.1% shows that the excellent analog and short-term properties of our perovskite memristor allow the hardware implementation of neuromorphic computing with a reduced training cost.

Neuromorphic Engineering: From Biological to Spike-Based Hardware Nervous Systems.

The human brain is a sophisticated, high-performance biocomputer that processes multiple complex tasks in parallel with high efficiency and remarkably low power consumption. Scientists have long been pursuing an artificial intelligence (AI) that can rival the human brain. Spiking neural networks based on neuromorphic computing platforms simulate the architecture and information processing of the intelligent brain, providing new insights for building AIs. The rapid development of materials engineering, device physics, chip integration, and neuroscience has led to exciting progress in neuromorphic computing with the goal of overcoming the von Neumann bottleneck. Herein, fundamental knowledge related to the structures and working principles of neurons and synapses of the biological nervous system is reviewed. An overview is then provided on the development of neuromorphic hardware systems, from artificial synapses and neurons to spike-based neuromorphic computing platforms. It is hoped that this review will shed new light on the evolution of brain-like computing.