Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfOx-based metal-ferroelectric-insulator-semiconductor stack.

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al2O3layer between the SiO2insulator and the pure-HfOxFE improves the read disturbance (2Vc = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.

A novel physical unclonable function (PUF) using 16 × 16 pure-HfOxferroelectric tunnel junction array for security applications.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfOx)-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.

Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing.

The progress of artificial intelligence and the development of large-scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low-power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high-density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest. In this study, an 8 × 16 memcapacitor crossbar array that combines the technological maturity of flash cells with the advantages of NAND flash array structure is presented. The analog properties of the array with high reliability are experimentally demonstrated, and vector-matrix multiplication with extremely low error is successfully performed. Additionally, with the capability of weight fine-tuning characteristics, a spiking neural network for CIFAR-10 classification via off-chip learning at the wafer level is implemented. These experimental results demonstrate a high level of accuracy of 92.11%, with less than a 1.13% difference compared to software-based neural networks (93.24%).

Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy.

Recently, ferroelectric tunnel junctions (FTJs) have gained extensive attention as possible candidates for emerging memory and synaptic devices for neuromorphic computing. However, the working principles of FTJs remain controversial despite the importance of understanding them. In this study, we demonstrate a comprehensive and accurate analysis of the working principles of a metal-ferroelectric-dielectric-semiconductor stacked FTJ using low-frequency noise (LFN) spectroscopy. In contrast to resistive random access memory, the 1/f noise of the FTJ in the low-resistance state (LRS) is approximately two orders of magnitude larger than that in the high-resistance state (HRS), indicating that the conduction mechanism in each state differs significantly. Furthermore, the factors determining the conduction of the FTJ in each state are revealed through a systematic investigation under various conditions, such as varying the electrical bias, temperature, and bias stress. In addition, we propose an efficient method to decrease the LFN of the FTJ in both the LRS and HRS using high-pressure forming gas annealing.

Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application.

In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed. The electrical characteristics, specifically the on-current (Ion), off-current (Ioff), and subthreshold swing (SS), were investigated as well. Hence, it is demonstrated here that incorporating a SOS substrate can improve both the self-heating characteristic and the SS at the same time. Therefore, enhanced logic devices are feasible if using an ONWFET with a SOS substrate. Examples include wearable devices and military and future aerospace applications achieved by the radiation-resistant material Al2O3 that has high thermal conductivity.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation.

In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). In order to investigate electrical and self-heating characteristics of the proposed devices, on-current, off-current, subthreshold swing (SS), and operating temperature were examined by using 3D TCAD simulator and compared with nanowire MOSFET (NW-MOSFET). As a result, a possibility of reducing off-current and operating temperature was demonstrated by using the ONWFET with 40% GCR. Therefore, the ONWFET can save power consumption and serve as low power application such as battery-powered portable electronic devices.

Investigation on Ambipolar Current Suppression Using a Stacked Gate in an L-shaped Tunnel Field-Effect Transistor.

L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current. Stacked gates can be easily implemented using the structural features of L-shaped TFET, and on- and off-current can be controlled separately by using different gates located near the source and the drain, respectively. As a result, the suppression of ambipolarity is observed with respect to work function difference between two gates by simulation of the band-to-band tunneling generation. Furthermore, the proposed device suppresses ambipolar current better than existing ambipolar current suppression methods. In particular, low drain resistance is achieved as there is no need to reduce drain doping, which leads to a 7% enhanced on-current. Finally, we present the fabrication method for a stacked gate L-shaped TFET.