Nanoscale Buckling of Ultrathin Low-k Dielectric Lines during Hard-Mask Patterning.

Stan, Gheorghe; Ciobanu, Cristian V; Levin, Igor; Yoo, Hui J; Myers, Alan; Singh, Kanwal; Jezewski, Christopher; Miner, Barbara; King, Sean W

Stan, Gheorghe; Ciobanu, Cristian V; Levin, Igor; Yoo, Hui J; Myers, Alan; Singh, Kanwal; Jezewski, Christopher; Miner, Barbara; King, Sean W.

Afiliação

Stan G; Material Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899, United States.
Ciobanu CV; Department of Mechanical Engineering, University of Maryland, College Park, Maryland 20742, United States.
Levin I; §Department of Mechanical Engineering, Colorado School of Mines, Golden, Colorado 80401, United States.
Yoo HJ; Material Measurement Laboratory, National Institute of Standards and Technology, Gaithersburg, Maryland 20899, United States.
Myers A; â¥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
Singh K; â¥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
Jezewski C; â¥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
Miner B; â¥Components Research, Intel Corporation, Hillsboro, Oregon 97124, United States.
King SW; â¥Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, United States.

Nano Lett ; 15(6): 3845-50, 2015 Jun 10.

Article em En | MEDLINE | ID: mdl-25950850

Palavras-chave

interconnect circuits; low-k dielectric patterns; nanoscale buckling

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Texto completo: 1 Coleções: 01-internacional Base de dados: MEDLINE Tipo de estudo: Prognostic_studies Idioma: En Revista: Nano Lett Ano de publicação: 2015 Tipo de documento: Article País de afiliação: Estados Unidos

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