Strain-Induced 2H to 1T' Phase Transition in Suspended MoTe2 Using Electric Double Layer Gating.

MoTe2 can be converted from the semiconducting (2H) phase to the semimetallic (1T') phase by several stimuli including heat, electrochemical doping, and strain. This type of phase transition, if reversible and gate-controlled, could be useful for low-power memory and logic. In this work, a gate-controlled and fully reversible 2H to 1T' phase transition is demonstrated via strain in few-layer suspended MoTe2 field effect transistors. Strain is applied by the electric double layer gating of a suspended channel using a single ion conducting solid polymer electrolyte. The phase transition is confirmed by simultaneous electrical transport and Raman spectroscopy. The out-of-plane vibration peak (A1g)─a signature of the 1T' phase─is observed when VSG ≥ 2.5 V. Further, a redshift in the in-plane vibration mode (E2g) is detected, which is a characteristic of a strain-induced phonon shift. Based on the magnitude of the shift, strain is estimated to be 0.2-0.3% by density functional theory. Electrically, the temperature coefficient of resistance transitions from negative to positive at VSG ≥ 2 V, confirming the transition from semiconducting to metallic. The approach to gate-controlled, reversible straining presented here can be extended to strain other two-dimensional materials, explore fundamental material properties, and introduce electronic device functionalities.

Impact of Large Gate Voltages and Ultrathin Polymer Electrolytes on Carrier Density in Electric-Double-Layer-Gated Two-Dimensional Crystal Transistors.

Electric-double-layer (EDL) gating can induce large capacitance densities (∼1-10 µF cm-2) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (VG) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate and therefore the time scale over which the channel can be doped. Typical thicknesses are on the order of micrometers, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) in terms of both physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore quantum capacitance, is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied VG without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which VG is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3 × 1013 cm-2 for electrons and 1.4 × 1013 cm-2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, poly(ethylene oxide) (PEO):CsClO4, is decreased from 1 µm to 10 nm and used to EDL gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm-1 µm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.