Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator.

We present the fabrication of 4 K-scale electrochemical random-access memory (ECRAM) cross-point arrays for analog neural network training accelerator and an electrical characteristic of an 8 × 8 ECRAM array with a 100% yield, showing excellent switching characteristics, low cycle-to-cycle, and device-to-device variations. Leveraging the advances of the ECRAM array, we showcase its efficacy in neural network training using the Tiki-Taka version 2 algorithm (TTv2) tailored for non-ideal analog memory devices. Through an experimental study using ECRAM devices, we investigate the influence of retention characteristics on the training performance of TTv2, revealing that the relative location of the retention convergence point critically determines the available weight range and, consequently, affects the training accuracy. We propose a retention-aware zero-shifting technique designed to optimize neural network training performance, particularly in scenarios involving cross-point devices with limited retention times. This technique ensures robust and efficient analog neural network training despite the practical constraints posed by analog cross-point devices.

Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.

A Load-Insensitive Hybrid LSK Back Telemetry System With Slope-Based Demodulation for Inductively Powered Biomedical Devices.

This paper presents a hybrid load-shift keying (LSK) modulation for a load-insensitive back telemetry system to realize near-constant voltage changes in a primary coil (L1) against a wide range of load variations. The hybrid-LSK-enabled full-wave rectifier enables the sequential combination of open- and short-coil functions for hybrid-LSK modulation in addition to wireless power conversion operation. Load-insensitive L1 voltage changes can be demodulated using the proposed slope- based demodulator, which utilizes the threshold slope of L1 voltage changes over the back data pulse width, enabling robust data recovery regardless of the load conditions. The 0.56-mm2 0.18-µm standard CMOS hybrid-LSK prototype demonstrated that the variation of L1 voltage changes could be minimized to 60 mV under load changes between 50 Ω and 50 kΩ at coil separation distance of 10 mm, achieving 88.2% reduction compared to the conventional short-coil LSK with 510 mV variation. The proposed back telemetry system also achieved a bit error rate (BER) of < 9.1 × 10-10 under load ranges from 50 Ω to 50 kΩ and data rate of 1 Mbps, ensuring reliable back data recovery against load variations.