Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique.

With the application of stitching technology in large-pixel-array CMOS image sensors, the problem of non-synchronized output signals from pixel array bilateral driver circuits has become progressively more serious and has led to the DC perforation of bilateral driver circuits, while conventional clock tree synchronization design methodology does not apply to stitching technology. Therefore, this paper analyses reasons for the inconsistency in the output signals of bilateral driving circuits and proposes a synchronous driving method applicable to stitching pixel arrays based on the idea of on-chip output signal delay detection and calibration. This method detects and corrects the non-synchrony of the row driver output signals on both sides according to changes in the operating environment of the chip. This method is characterized by a simple structure and high reliability. Finally, based on the 55 nm stitching process, simulations are carried out in a CMOS image sensor with a chip area of 77 mm × 84 mm to verify that this method is feasible. This large image sensor with a 150 M pixel array has a frame rate of over 10 FPS.

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors.

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 µm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 µm pixels and channels B3-B6 are 20 µm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

Investigating a Machine Learning Approach to Predicting White Pixel Defects in Wafers-A Case Study of Wafer Fabrication Plant F.

CMOS image sensor (CIS) semiconductor products are integral to mobile phones and photographic devices, necessitating ongoing enhancements in efficiency and quality for superior photographic outcomes. The presence of white pixels serves as a crucial metric for assessing CIS product performance, primarily arising from metal impurity contamination during the wafer production process or from defects introduced by the grinding blade process. While immediately addressing metal impurity contamination during production presents challenges, refining the handling of defects attributed to grinding blade processing can notably mitigate white pixel issues in CIS products. This study zeroes in on silicon wafer manufacturers in Taiwan, analyzing white pixel defects reported by customers and leveraging machine learning to pinpoint and predict key factors leading to white pixel defects from grinding blade operations. Such pioneering practical studies are rare. The findings reveal that the classification and regression tree (CART) and random forest (RF) models deliver the most accurate predictions (95.18%) of white pixel defects caused by grinding blade operations in a default parameter setting. The analysis further elucidates critical factors like grinding load and torque, vital for the genesis of white pixel defects. The insights garnered from this study aim to arm operators with proactive measures to diminish the potential for customer complaints.

Millimeter-Wave Band Electro-Optical Imaging System Using Polarization CMOS Image Sensor and Amplified Optical Local Oscillator Source.

In this study, we developed and demonstrated a millimeter-wave electric field imaging system using an electro-optic crystal and a highly sensitive polarization measurement technique using a polarization image sensor, which was fabricated using a 0.35-µm standard CMOS process. The polarization image sensor was equipped with differential amplifiers that amplified the difference between the 0° and 90° pixels. With the amplifier, the signal-to-noise ratio at low incident light levels was improved. Also, an optical modulator and a semiconductor optical amplifier were used to generate an optical local oscillator (LO) signal with a high modulation accuracy and sufficient optical intensity. By combining the amplified LO signal and a highly sensitive polarization imaging system, we successfully performed millimeter-wave electric field imaging with a spatial resolution of 30×60 µm at a rate of 1 FPS, corresponding to 2400 pixels/s.

Characterization of Partial Discharges in Dielectric Oils Using High-Resolution CMOS Image Sensor and Convolutional Neural Networks.

In this work, an exhaustive analysis of the partial discharges that originate in the bubbles present in dielectric mineral oils is carried out. To achieve this, a low-cost, high-resolution CMOS image sensor is used. Partial discharge measurements using that image sensor are validated by a standard electrical detection system that uses a discharge capacitor. In order to accurately identify the images corresponding to partial discharges, a convolutional neural network is trained using a large set of images captured by the image sensor. An image classification model is also developed using deep learning with a convolutional network based on a TensorFlow and Keras model. The classification results of the experiments show that the accuracy achieved by our model is around 95% on the validation set and 82% on the test set. As a result of this work, a non-destructive diagnosis method has been developed that is based on the use of an image sensor and the design of a convolutional neural network. This approach allows us to obtain information about the state of mineral oils before breakdown occurs, providing a valuable tool for the evaluation and maintenance of these dielectric oils.

Synergistic Radiation Effects in PPD CMOS Image Sensors Induced by Neutron Displacement Damage and Gamma Ionization Damage.

The synergistic effects on the 0.18 µm PPD CISs induced by neutron displacement damage and gamma ionization damage are investigated. The typical characterizations of the CISs induced by the neutron displacement damage and gamma ionization damage are presented separately. The CISs are irradiated by reactor neutron beams up to 1 × 1011 n/cm2 (1 MeV neutron equivalent fluence) and 60Co γ-rays up to the total ionizing dose level of 200 krad(Si) with different sequential order. The experimental results show that the mean dark signal increase in the CISs induced by reactor neutron radiation has not been influenced by previous 60Co γ-ray radiation. However, the mean dark signal increase in the CISs induced by 60Co γ-ray radiation has been remarkably influenced by previous reactor neutron radiation. The synergistic effects on the PPD CISs are discussed by combining the experimental results and the TCAD simulation results of radiation damage.

A CMOS Image Sensor Dark Current Compensation Using In-Pixel Temperature Sensors.

This paper presents a novel technique for dark current compensation of a CMOS image sensor (CIS) by using in-pixel temperature sensors (IPTSs) over a temperature range from -40 °C to 90 °C. The IPTS makes use of the 4T pixel as a temperature sensor. Thus, the 4T pixel has a double functionality, either as a pixel or as a temperature sensor. Therefore, the dark current compensation can be carried out locally by generating an artificial dark reference frame from the temperature measurements of the IPTSs and the temperature behavior of the dark current (previously calibrated). The artificial dark current frame is subtracted from the actual images to reduce/cancel the dark signal level of the pictures. In a temperature range from -40 °C to 90 °C, results show that the temperature sensors have an average temperature coefficient (TC) of 1.15 mV/°C with an inaccuracy of ±0.55 °C. Parameters such as conversion gain, gain of the amplifier, and ADC performance have been analyzed over temperature. The dark signal can be compensated in the order of 80% in its median value, and the nonuniformity is reduced in the order of 55%.

Modeling Signal-to-Noise Ratio of CMOS Image Sensors with a Stochastic Approach under Non-Stationary Conditions.

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal-oxide-semiconductor (CMOS) image sensors (APS), assuming stationary conditions was recently presented in this journal. In this study, we extend the stochastic approach to non-stationary conditions. Non-stationary conditions occur in gated imaging applications. This new stochastic model, which is based on fundamental physical considerations, enlightens us with new insights into gated CMOS imaging, regardless of the sensor. The Signal-to-Noise Ratio (SNR) is simulated, allowing optimized performance. The conversion gain should be determined under stationary conditions.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor.

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 µW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A Numerical Method of Aligning the Optical Stacks for All Pixels.

Reducing performance verification time is significant in product launch and production costs. This is especially true because aligning the optical stacks of off-axis pixels is a time-consuming task, but it is important to maintain sensitivity. In this paper, a numerical method to align the optical stacks of off-axis pixels is suggested in order to reduce performance test time. The components of the numerical method are the optical stack height, refractive index, and chief ray angle in order to calculate the optical stacks' optimal shift distance. The proposed method was investigated to confirm effectiveness by using optical simulation. The sub-micron backside illumination (BSI) pixels were simulated, having 2 × 2 microlens, quad-color filter array, and in-pixel deep trench isolation (DTI). Moreover, the proposed method was evaluated for various pixel pitches, microlens shapes, and CRAs. As a result, the optical stacks were optimized by using the numerical method and validated via optical simulation. Therefore, the proposed numerical method is expected to help reduce the time and cost.

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor.

A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for electron-referred noise floor. However, LOFIC-CMOS image sensor requires a two-channel read-out chain for LCG and HCG signals whose polarities are inverted. In order to provide an area-efficient LOFIC-CMOS image sensor, a one-channel read-out chain that can process both HCG and LCG signals is presented in this paper. An up/down double-sampling circuit composed of an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals can reduce the area of the read-out chain by half compared to the conventional two-channel read-out chain. A test chip is fabricated in a 0.18 µm CMOS process with a metal-insulator-metal (MIM) capacitor, achieving a readout noise of 130 µVrms for the HCG signal and 1.19 V for the LCG input window. The performance is equivalent to 103 dB of the dynamic range with our previous LOFIC pixel in which HCG and LCG conversion gains are, respectively, 160 µV/e- and 10 µV/e-.

Design of Low-Noise CMOS Image Sensor Using a Hybrid-Correlated Multiple Sampling Technique.

We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 µm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.

N-Channel MOSFET Reliability Issue Induced by Visible/Near-Infrared Photons in Image Sensors.

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy.

Pion Detection Using Single Photon Avalanche Diodes.

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of incident high-energy pions at 120 GeV, minimally ionizing, which complements the variety of ionizing radiation that can be detected with CMOS SPADs.

Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity.

In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement.

Design of a CMOS Image Sensor with Bi-Directional Gamma-Corrected Digital-Correlated Double Sampling.

We present a 640 × 480 CMOS image sensor (CIS) with in-circuit bi-directional gamma correction with a proposed digital-correlated double sampling (CDS) structure. To operate the gamma correction in the CIS, the transfer function of the analog-to-digital converter can be changed by controlling the clock frequency of the counter using analog CDS. However, the analog CDS is vulnerable to capacitor mismatch, clock feedthrough, etc. Therefore, we propose a digital-CDS method with a hold-and-go counter structure to operate the bi-directional gamma correction in the CIS. The proposed CIS achieves a 10-bit resolution using a global log-exponential counter and configurable column reset counter with a resolution of 8/9 bits. The sensor was fabricated in a 0.11 µm CIS process, and the full chip area was 5.9 mm × 5.24 mm. The measurement results showed a maximum SNR improvement of 10.41% with the proposed bi-directional gamma-corrected digital-CDS with the hold-and-go counter. The total power consumption was 6.3 mW at a rate of 16.6 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.

Random Telegraph Noise Degradation Caused by Hot Carrier Injection in a 0.8 µm-Pitch 8.3Mpixel Stacked CMOS Image Sensor.

In this work, the degradation of the random telegraph noise (RTN) and the threshold voltage (Vt) shift of an 8.3Mpixel stacked CMOS image sensor (CIS) under hot carrier injection (HCI) stress are investigated. We report for the first time the significant statistical differences between these two device aging phenomena. The Vt shift is relatively uniform among all the devices and gradually evolves over time. By contrast, the RTN degradation is evidently abrupt and random in nature and only happens to a small percentage of devices. The generation of new RTN traps by HCI during times of stress is demonstrated both statistically and on the individual device level. An improved method is developed to identify RTN devices with degenerate amplitude histograms.

A 316MP, 120FPS, High Dynamic Range CMOS Image Sensor for Next Generation Immersive Displays.

We present a 2D-stitched, 316MP, 120FPS, high dynamic range CMOS image sensor with 92 CML output ports operating at a cumulative date rate of 515 Gbit/s. The total die size is 9.92 cm × 8.31 cm and the chip is fabricated in a 65 nm, 4 metal BSI process with an overall power consumption of 23 W. A 4.3 µm dual-gain pixel has a high and low conversion gain full well of 6600e- and 41,000e-, respectively, with a total high gain temporal noise of 1.8e- achieving a composite dynamic range of 87 dB.

Reduction of White Spot Defects in CMOS Image Sensors Fabricated Using Epitaxial Silicon Wafer with Proximity Gettering Sinks by CH2P Molecular Ion Implantation.

Using a new implantation technique with multielement molecular ions consisting of carbon, hydrogen, and phosphorus, namely, CH2P molecular ions, we developed an epitaxial silicon wafer with proximity gettering sinks under the epitaxial silicon layer to improve the gettering capability for metallic impurities. A complementary metal-oxide-semiconductor (CMOS) image sensor fabricated with this novel epitaxial silicon wafer has a markedly reduced number of white spot defects, as determined by dark current spectroscopy (DCS). In addition, the amount of nickel impurities gettered in the CH2P-molecular-ion-implanted region of this CMOS image sensor is higher than that gettered in the C3H5-molecular-ion-implanted region; and this implanted region is formed by high-density black pointed defects and deactivated phosphorus after epitaxial growth. From the obtained results, the CH2P-molecular-ion-implanted region has two types of complexes acting as gettering sinks. One includes carbon-related complexes such as aggregated C-I, and the other includes phosphorus-related complexes such as P4-V. These complexes have a high binding energy to metallic impurities. Therefore, CH2P-molecular-ion-implanted epitaxial silicon wafers have a high gettering capability for metallic impurities and contribute to improving the device performance of CMOS image sensors. (This manuscript is an extension from a paper presented at the 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM 2022)).

A CMOS Image Sensor Based Refractometer without Spectrometry.

The refractive index (RI), an important optical property of a material, is measured by commercial refractometers in the food, agricultural, chemical, and manufacturing industries. Most of these refractometers must be equipped with a prism for light dispersion, which drastically limits the design and size of the refractometer. Recently, there have been several reports on the development of a surface plasmon resonance (SPR)-based RI detector, which is characterized by its high sensitivity and simplicity. However, regardless of the prism, an expensive spectrometer is required to analyze the resonance wavelength or angle of incidence. This paper proposes a method that eliminates the need for the prism and other conventional spectrometer components. For this purpose, total internal reflection SPR technology was used on an Ag thin film, and RI analysis was combined with a lens-free CMOS image sensor or a smartphone camera. A finite-difference time-domain (FDTD) numerical simulation was performed to evaluate the relationship between the output power intensity and Ag film thickness for different RIs at three wavelengths of commercial light-emitting diodes (LEDs). The maximum sensitivity of -824.54 RIU-1 was achieved with AG20 at an incident wavelength of 559 nm. Due to its simple design and cost effectiveness, this prism-less, SPR-based refractometer combined with a lens-free CMOS image sensor or a smartphone could be a superior candidate for a point-of-care device that can determine the RIs of various analytes in the field of biological or chemical sensing.