High-Dimensional Physical Reservoir with Back-End-of-Line-Compatible Tin Monoxide Thin-Film Transistor.

This work demonstrates a physical reservoir using a back-end-of-line compatible thin-film transistor (TFT) with tin monoxide (SnO) as the channel material for neuromorphic computing. The electron trapping and time-dependent detrapping at the channel interface induce the SnO·TFT to exhibit fading memory and nonlinearity characteristics, the critical assets for physical reservoir computing. The three-terminal configuration of the TFT allows the generation of higher-dimensional reservoir states by simultaneously adjusting the bias conditions of the gate and drain terminals, surpassing the performances of typical two-terminal-based reservoirs such as memristors. The high-dimensional SnO TFT reservoir performs exceptionally in two benchmark tests, achieving a 94.1% accuracy in Modified National Institute of Standards and Technology handwritten number recognition and a normalized root-mean-square error of 0.089 in Mackey-Glass time-series prediction. Furthermore, it is suitable for vertical integration because its fabrication temperature is <250 °C, providing the benefit of achieving a high integration density.

Review of Semiconductor Flash Memory Devices for Material and Process Issues.

Vertically integrated NAND (V-NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176-layer-stacked V-NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400-500) due to the total allowable chip thickness, which will be reached within 6-7 years. This review summarizes the current status and critical challenges of charge-trap-based flash memory devices, with a focus on the material (floating-gate vs charge-trap-layer), array-level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell-level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.