RESUMO
Design technology co-optimization (DTCO) is a potential approach to tackle the escalating expenses and complexities associated with pitch scaling. This strategy offers a promising solution by minimizing the required design dimensions and mitigating the pitch scaling trend. It is worth noting that lithography has played a significant role in dimensional scaling over time. This paper proposes a DTCO flow to reduce the impact of the process variation (PV) band and edge placement error (EPE). First, we performed the digital back-end design of the high-performance processor and got the test layout; second, we executed timing analysis on the test layout to get the critical path net that affects the chip performance; third, we proposed the timing-aware optimized optical proximity correction (OPC) method to optimize the PV band and EPE by adjusting the weights of critical path net merit points, optimizing the generation of the sub-resolution assistant feature, giving tighter EPE specs for merit points on the critical path net, and placing denser merit points as well as denser breakpoints for the critical path net to obtain greater freedom in the OPC process. Finally, it is verified that our proposed DTCO process can significantly reduce the EPE and lead to a slight decrease in the PV band of the chip while maintaining the same process windows.