Recent Advances In Silicon Carbide Chemical Mechanical Polishing Technologies.

Chemical mechanical polishing (CMP) is a well-known technology that can produce surfaces with outstanding global planarization without subsurface damage. A good CMP process for Silicon Carbide (SiC) requires a balanced interaction between SiC surface oxidation and the oxide layer removal. The oxidants in the CMP slurry control the surface oxidation efficiency, while the polishing mechanical force comes from the abrasive particles in the CMP slurry and the pad asperity, which is attributed to the unique pad structure and diamond conditioning. To date, to obtain a high-quality as-CMP SiC wafer, the material removal rate (MRR) of SiC is only a few micrometers per hour, which leads to significantly high operation costs. In comparison, conventional Si CMP has the MRR of a few micrometers per minute. To increase the MRR, improving the oxidation efficiency of SiC is essential. The higher oxidation efficiency enables the higher mechanical forces, leading to a higher MRR with better surface quality. However, the disparity on the Si-face and C-face surfaces of 4H- or 6H-SiC wafers greatly increases the CMP design complexity. On the other hand, integrating hybrid energies into the CMP system has proven to be an effective approach to enhance oxidation efficiency. In this review paper, the SiC wafering steps and their purposes are discussed. A comparison among the three configurations of SiC CMP currently used in the industry is made. Moreover, recent advances in CMP and hybrid CMP technologies, such as Tribo-CMP, electro-CMP (ECMP), Fenton-ECMP, ultrasonic-ECMP, photocatalytic CMP (PCMP), sulfate-PCMP, gas-PCMP and Fenton-PCMP are reviewed, with emphasis on their oxidation behaviors and polishing performance. Finally, we raise the importance of post-CMP cleaning and make a summary of the various SiC CMP technologies discussed in this work.

State-of-the-Art ß-Ga2O3 Field-Effect Transistors for Power Electronics.

Due to the emergence of electric vehicles, power electronics have become the new focal point of research. Compared to commercialized semiconductors, such as Si, GaN, and SiC, power devices based on ß-Ga2O3 are capable of handling high voltages in smaller dimensions and with higher efficiencies, because of the ultrawide bandgap (4.9 eV) and large breakdown electric field (8 MV cm-1). Furthermore, the ß-Ga2O3 bulk crystals can be synthesized by the relatively low-cost melt growth methods, making the single-crystal substrates and epitaxial layers readily accessible for fabricating high-performance power devices. In this article, we first provide a comprehensive review on the material properties, crystal growth, and deposition methods of ß-Ga2O3, and then focus on the state-of-the-art depletion mode, enhancement mode, and nanomembrane field-effect transistors (FETs) based on ß-Ga2O3 for high-power switching and high-frequency amplification applications. In the meantime, device-level approaches to cope with the two main issues of ß-Ga2O3, namely, the lack of p-type doping and the relatively low thermal conductivity, will be discussed and compared.