Comparison of Lumped Oscillator Model and Energy Participation Ratio Methods in Designing Two-Dimensional Superconducting Quantum Chips.

Over the past two decades, superconducting quantum circuits have become one of the essential platforms for realizing quantum computers. The Hamiltonian of a superconducting quantum circuit system is the key to describing the dynamic evolution of the system. For this reason, various methods for analyzing the Hamiltonian of a superconducting quantum circuit system have been proposed, among which the LOM (Lumped Oscillator Model) and the EPR (Energy Participation Ratio) methods are the most popular ones. To analyze and improve the design methods of superconducting quantum chips, this paper compares the similarities and differences of the LOM and the EPR quantification methods. We verify the applicability of these two theoretical approaches to the design of 2D transmon quantum chips. By comparing the theoretically simulated results and the experimentally measured data at extremely low temperature, the errors between the theoretical calculation and observed measurement values of the two methods were summarized. Results show that the LOM method has more parameter outputs in data diversity and the qubit frequency calculation in LOM is more accurate. The reason is that in LOM more coupling between different systems are taken into consideration. These analyses would have reference significance for the design of superconducting quantum chips.

Suppressing the Dielectric Loss in Superconducting Qubits through Useful Geometry Design.

Dielectric loss from different interfacial layers in the superconducting circuit and from external environment may cause superconducting qubit decoherence. Compared to modeling the entire device at once with a numerical solver, quantitatively formulating the dielectric loss can both describe all loss mechanisms and make the optimization more transparent. In this paper, we first analyze the expression formula of dielectric loss, and obtain a design scheme that can reduce the dielectric loss of qubits. That is, we replace the straight junction wires with the tapered junction wires. Based on this scheme, we perform a simulation to optimize the design of junction wires. Finally, a real experiment is conducted to verify our design. The results show that both the T1 time and T2 time of qubits are significantly improved.