Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier.

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.

Fabrication of nano-sized magnetic tunnel junctions using lift-off process assisted by atomic force probe tip.

We present a fabrication method for nano-scale magnetic tunnel junctions (MTJs), employing e-beam lithography and lift-off process assisted by the probe tip of atomic force microscope (AFM). It is challenging to fabricate nano-sized MTJs on small substrates because it is difficult to use chemical mechanical planarization (CMP) process. The AFM-assisted lift-off process enables us to fabricate nano-sized MTJs on small substrates (12.5 mm x 12.5 mm) without CMP process. The e-beam patterning has been done using bi-layer resist, the poly methyl methacrylate (PMMA)/ hydrogen silsesquioxane (HSQ). The PMMA/HSQ resist patterns are used for both the etch mask for ion milling and the self-aligned mask for top contact formation after passivation. The self-aligned mask buried inside a passivation oxide layer, is readily lifted-off by the force exerted by the probe tip. The nano-MTJs (160 nm x 90 nm) fabricated by this method show clear current-induced magnetization switching with a reasonable TMR and critical switching current density.

Simulation study of the scaling behavior of top-gated carbon nanotube field effect transistors.

Device simulations on three-dimensional top-gated carbon nanotube field effect transistors (CNTFETs) have been performed by considering the quantum transport described in the framework of non-equilibrium Green's function method. Device characteristics of various top-gated CNTFETs, such as Schottky-barrier CNTFETs, CNTFETs with doped source and drain, and tunnel-FET-like CNTFETs, have been examined, focusing on their scaling behavior as the channel length is ultimately reduced down to a few nanometers. Comparison with coaxially-gated devices is also made.

Vertical and Lateral Copper Transport through Graphene Layers.

A different mechanism was found for Cu transport through multi-transferred single-layer graphene serving as diffusion barriers on the basis of time-dependent dielectric breakdown tests. Vertical and lateral transport of Cu dominates at different stress electric field regimes. The classic E-model was modified to project quantitatively the effectiveness of the graphene Cu diffusion barrier at low electric field based on high-field accelerated stress data. The results are compared to industry-standard Cu diffusion barrier material TaN. 3.5 Å single-layer graphene shows the mean time-to-fail comparable to 4 nm TaN, while two-time and three-time transferred single-layer graphene stacks give 2× and 3× improvements, respectively, compared to single-layer graphene at a 0.5 MV/cm electric field. The influences of graphene grain boundaries on Cu vertical transport through the graphene layers are explored, revealing that large-grain (10-15 µm) single-layer graphene gives a 2 orders of magnitude longer lifetime than small-grain (2-3 µm) graphene. As a result, it is more effective to further enhance graphene barrier reliability by improving single-layer graphene quality through increasing grain sizes or using single-crystalline graphene than just by increasing thickness through multi-transfer. These results may also be applied for graphene as barriers for other metals.

Selective metal deposition at graphene line defects by atomic layer deposition.

One-dimensional defects in graphene have a strong influence on its physical properties, such as electrical charge transport and mechanical strength. With enhanced chemical reactivity, such defects may also allow us to selectively functionalize the material and systematically tune the properties of graphene. Here we demonstrate the selective deposition of metal at chemical vapour deposited graphene's line defects, notably grain boundaries, by atomic layer deposition. Atomic layer deposition allows us to deposit Pt predominantly on graphene's grain boundaries, folds and cracks due to the enhanced chemical reactivity of these line defects, which is directly confirmed by transmission electron microscopy imaging. The selective functionalization of graphene defect sites, together with the nanowire morphology of deposited Pt, yields a superior platform for sensing applications. Using Pt-graphene hybrid structures, we demonstrate high-performance hydrogen gas sensors at room temperature and show its advantages over other evaporative Pt deposition methods, in which Pt decorates the graphene surface non-selectively.