RESUMEN
The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct VTHs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5â ©104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆VTH of 14 V and retained memory currents for 103 s with IM,ON/IM,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.
RESUMEN
We suggest a facile method to reduce the surface roughness of the ferroelectric polymer insulator to enhance the electrical performance of the ferroelectric field effect memory transistors (FeFET). Ferroelectric-dielectric mixed buffer layer was used to reduce the high surface roughness of the single layer ferroelectric polymer insulator. The FeFET with mixed buffer bilayer (BL-FeFET) showed more than 25 times higher on-current (3.40 µA) compared with single layer FeFET (130 nA). The BL-FeFET showed enhanced memory retention, higher memory on-off ratio than the conventional single layer FeFET (SL-FeFET). The enhancement of the electrical performance of the BL-FeFET can be attributed to the smoothening of the rough needle-like grain surface morphology of the ferroelectric polymer insulator in the SL-FeFET. This process of mixed buffer polymer insulator may provide a technological method for production of high-performance nonvolatile FeFET memory devices.
RESUMEN
We presented further analysis to explain how the surface morphology influence the mobility of the organic thin film transistors with gate insulator having large undulated surface (GU-OTFTs) and introduced a new parameter in order to clearly understand the relation between surface roughness and field-effect mobility. The average of the slope between two adjacent points on the surface of a gate insulator, or effective surface smoothness (ES), was closely investigated. A smooth-contact-pressing (SCP) process affected the surface smoothness of the P(VDF-TrFE) insulator with a significant change in root-mean-square roughness (Zrms). It was found that the ES gives better explanation for the variation of the field-effect mobility of the GU-OTFTs than the Zrms.
RESUMEN
We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 104. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.
RESUMEN
We demonstrated an organic and oxide hybrid CMOS inverter with the solution-processed semiconductor and source/drain electrodes. For the solution-processed n- and p-type semiconductor, InGaZnO solution and TIPS-pentacene/PαMS blend were spin-coated respectively while Silver ink and PEDOT:PSS solution were drop-casted with the help of the bank to serve as source/drain electrodes. The InGaZnO and the TIPS-pentacene transistors show typical n- and p-type transistor operations with low off-current. Based on the combination of the solution-processed n- and p-type transistors, full-swing characteristic curve with low static current of the hybrid CMOS were obtained.