A 108 dB DR Δ∑-∑M Front-End With 720 mVpp Input Range and >±300 mV Offset Removal for Multi-Parameter Biopotential Recording.

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2nd-order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-µm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mVpp. The measured input-referred noise is 0.98 µVrms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels.

Large-scale in vivo electrophysiology requires tools that enable simultaneous recording of multiple brain regions at single-neuron level. This calls for the design of more compact neural probes that offer even larger arrays of addressable sites and high channel counts. With this aim, we present in this paper a quad-shank approach to integrate as many as 5,120 sites on a single probe. Compact fully-differential recording channels were designed using a single-gain-stage neural amplifier with a 14-bit ADC, achieving a mean input-referred noise of 7.44 µVrms in the action-potential band and 7.65 µVrms in the local-field-potential band, a mean total harmonic distortion of 0.17% at 1 kHz and a mean input-referred offset of 169 µV. The probe base incorporates 384 channels with on-chip power management, reference-voltage generation and digital control, thus achieving the highest level of integration in a neural probe and excellent channel-to-channel uniformity. Therefore, no calibration or external circuitry are required to achieve the above-mentioned performance. With a total area of 2.2 × 8.67 mm2 and a power consumption of 36.5 mW, the presented probe enables full-system miniaturization for acute or chronic use in small rodents.

Safety ensuring retinal prosthesis with precise charge balance and low power consumption.

Ensuring safe operation of stimulators is the most important issue in neural stimulation. Safety, in terms of stimulators' electrical performances, can be related mainly to two factors; the zero-net charge transfer to tissue and the heat generated by power dissipation at tissue. This paper presents a safety ensuring neuro-stimulator for retinal vision prostheses, featuring precise charge balancing capability and low power consumption, using a 0.35 µm HV (high voltage) CMOS process. Also, the required matching accuracy of the biphasic current pulse for safe stimulation is mathematically derived. Accurate charge balance is achieved by employing a dynamic current mirror at the output of a stimulator. In experiments, using a simple electrode model (a resistor (R) and a capacitor (C) in parallel), the proposed stimulator ensures less than 30 nA DC current flowing into tissue over all stimulation current ranges (32 µA-1 mA), without shorting. With shorting enabled, further reduction is achieved down to 1.5 nA. Low power consumption was achieved by utilising small bias current, sharing of key biasing blocks, and utilising a short duty cycle for stimulation. Less than 30 µW was consumed during stand-by mode, mostly by bias circuitry.

Required matching accuracy of biphasic current pulse in multi-channel current mode bipolar stimulation for safety.

In neural stimulation, a current mode stimulation is preferred to a voltage mode stimulation, as it has more control over injecting charge into tissue. A matched biphasic current pulse is often employed in current mode stimulation. For safe neural stimulation, in other words, to ensure zero-net charge transfer (charge balance) into tissue, it is required to utilise a precisely matched biphasic current pulse. Mismatch in the biphasic current pulse causes residual charge on stimulating electrodes during stimulation, which will induce DC current flowing into tissue, possibly leading to tissue damage. In this paper, we derive mathematical expressions of the required matching accuracy on the biphasic current pulse under 4 different situations to ensure a safe neural stimulation; 1) single channel stimulation without shorting, 2) single channel stimulation with shorting, 3) multi-channel stimulation without shorting and 4) multi-channel stimulation with shorting.

A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis.

In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator front-end to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476µA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.