Three-dimensional wavelength-division multiplexing interconnects based on a low-loss SixNy arrayed waveguide grating.

We fabricate three-dimensional wavelength-division multiplexing (3D-WDM) interconnects comprising three SixNy layers using a CMOS-compatible process. In these interconnects, the optical signals are coupled directly to a SixNy grating coupler in the middle SixNy layer and demultiplexed by a 1 × 4 SixNy array waveguide grating (AWG). The demultiplexed optical signals are interconnected from the middle SixNy layer to the bottom and top SixNy layers by four SiOxNy interlayer couplers. A low insertion loss and low crosstalk are achieved in the AWG. The coupling losses of the SiOxNy interlayer couplers and SixNy grating coupler are ∼1.52 dB and ∼4.2 dB, respectively.

Performance improvement in silicon arrayed waveguide grating by suppression of scattering near the boundary of a star coupler.

We investigate the reduction of transition loss across the star coupler boundary in a silicon arrayed waveguide grating (AWG) by suppressing multimode generation and scattering near the boundary of a star coupler. Eight-channel silicon AWGs were designed with optimal conditions based on enhanced field matching in combination with ultrashallow etched structures. The fabricated AWG demonstrates an insertion loss down to 0.63 dB with a cross talk of -23 to -25.3 dB, exhibiting ~0.8 dB improvement of insertion loss and ~4 dB improvement of cross talk compared to the Si AWG fabricated with a conventional double-etch technique.

Monolithic InP strictly non-blocking 8×8 switch for high-speed WDM optical interconnection.

A strictly non-blocking 8 × 8 switch for high-speed WDM optical interconnection is realized on InP by using the phased-array scheme for the first time. The matrix switch architecture consists of over 200 functional devices such as star couplers, phase-shifters and so on without any waveguide cross-section. We demonstrate ultra-broad optical bandwidth covering the entire C-band through several Input/Output ports combination with extinction ratio performance of more than 20dB. Also, nanoseconds reconfiguration time was successfully achieved by dynamic switching experiment. Error-free transmission was verified for 40-Gbps (10-Gbps × 4ch) WDM signal.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.