Atomic-scale mapper for superlattice photodetectors analysis.

In this work, a new Python-based tool for atomic-scale mapping of high-angle annular dark-field (HAADF) and annular bright-field (ABF) scanning transmission electron microscopy (STEM) images using the Z-contrast method is introduced, aimed to help in the analysis of superlattice layers' composition, and in the determination of material of interfaces. The operation principle of the program, as well as specific examples of use, are explained in many details. Good customization flexibility using the user-friendly graphical user interface (GUI), allows the processing of a wide range of images, demonstrating a decent accuracy of coordinates extraction and performance.

Comparative advantages of a type-II superlattice barrier over an AlGaSb barrier for enhanced performance of InAs/GaSb LWIR nBn photodetectors.

The barrier layer in InAs/GaSb LWIR nBn detector is usually composed of AlGaSb alloy, which has a non-negligible valence band offset and is sensitive to chemical solutions. In this work, we investigated a type-II superlattice (T2SL) barrier that is homogeneous with the T2SL absorber layer in order to resolve these drawbacks of the AlGaSb barrier. The lattice mismatch of the T2SL barrier was smaller than that of the AlGaSb barrier. At -70mV and 80 K, the dark current density and the noise equivalent temperature difference of the nBn devices with the T2SL barrier were 4.4×10-6A/cm2 and 33 mK, respectively.

3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks.

Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III-V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (αp/αd = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics.