Ultrathin ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Roadmap on emerging hardware and technology for machine learning.

Recent progress in artificial intelligence is largely attributed to the rapid development of machine learning, especially in the algorithm and neural network models. However, it is the performance of the hardware, in particular the energy efficiency of a computing system that sets the fundamental limit of the capability of machine learning. Data-centric computing requires a revolution in hardware systems, since traditional digital computers based on transistors and the von Neumann architecture were not purposely designed for neuromorphic computing. A hardware platform based on emerging devices and new architecture is the hope for future computing with dramatically improved throughput and energy efficiency. Building such a system, nevertheless, faces a number of challenges, ranging from materials selection, device optimization, circuit fabrication and system integration, to name a few. The aim of this Roadmap is to present a snapshot of emerging hardware technologies that are potentially beneficial for machine learning, providing the Nanotechnology readers with a perspective of challenges and opportunities in this burgeoning field.

Two-dimensional gallium nitride realized via graphene encapsulation.

The spectrum of two-dimensional (2D) and layered materials 'beyond graphene' offers a remarkable platform to study new phenomena in condensed matter physics. Among these materials, layered hexagonal boron nitride (hBN), with its wide bandgap energy (∼5.0-6.0 eV), has clearly established that 2D nitrides are key to advancing 2D devices. A gap, however, remains between the theoretical prediction of 2D nitrides 'beyond hBN' and experimental realization of such structures. Here we demonstrate the synthesis of 2D gallium nitride (GaN) via a migration-enhanced encapsulated growth (MEEG) technique utilizing epitaxial graphene. We theoretically predict and experimentally validate that the atomic structure of 2D GaN grown via MEEG is notably different from reported theory. Moreover, we establish that graphene plays a critical role in stabilizing the direct-bandgap (nearly 5.0 eV), 2D buckled structure. Our results provide a foundation for discovery and stabilization of 2D nitrides that are difficult to prepare via traditional synthesis.

ON-state evolution in lateral and vertical VO2 threshold switching devices.

We report the results of finite element simulations of the ON state characteristic of VO2-based threshold switching devices and compare the results with experimental data. The model is based on thermally induced threshold switching (thermal runaway) and successfully reproduces the I-V characteristics showing the formation and growth of the conductive filament in the ON state. Furthermore, we compare the I-V characteristics for two VO2 films with different electrical conductivities in the insulating and metallic phases as well as those based on TaO x and NbO x functional layers.

Electrically driven reversible insulator-metal phase transition in 1T-TaS2.

In this work, we demonstrate abrupt, reversible switching of resistance in 1T-TaS2 using dc and pulsed sources, corresponding to an insulator-metal transition between the insulating Mott and equilibrium metallic states. This transition occurs at a constant critical resistivity of 7 mohm-cm regardless of temperature or bias conditions and the transition time is significantly smaller than abrupt transitions by avalanche breakdown in other small gap Mott insulating materials. Furthermore, this critical resistivity corresponds to a carrier density of 4.5 × 10(19) cm(-3), which compares well with the critical carrier density for the commensurate to nearly commensurate charge density wave transition. These results suggest that the transition is facilitated by a carrier driven collapse of the Mott gap in 1T-TaS2, which results in fast (3 ns) switching.

Electron transport in multigate In x Ga 1-x as nanowire FETs: from diffusive to ballistic regimes at room temperature.

The III-V semiconductors such as In x Ga 1-x As (x = 0.53-0.70) have attracted significant interest in the context of low power digital complementary metal-oxide-semiconductor (CMOS) technology due to their superior transport properties. However, top-down patterning of III-V semiconductor thin films into strongly confined quasi-one-dimensional (1D) nanowire geometries can potentially degrade the transport properties. To date, few reports exist regarding transport measurement in multigate nanowire structures. In this work, we report a novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs). We demonstrate multigate NWFETs integrated with probe electrodes in Hall Bridge geometry to enable four-point measurements of both longitudinal and transverse resistance. This allows for the first time accurate extraction of Hall mobility and its dependence on carrier concentration in III-V NWFETs. Furthermore, it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility. We characterize the mobility for various nanowire widths down to 40 nm and observe a monotonic reduction in mobility compared to planar devices. Despite this reduction, III-V NWFET mobility is shown to outperform state-of-the-art strained silicon NWFETs. Finally, we demonstrate evidence of room -temperature ballistic transport, a desirable property in the context of short channel transistors, in strongly confined III-V nanowire junctions using magneto-transport measurements in a nanoscale Hall-cross structure.

Hubbard gap modulation in vanadium dioxide nanoscale tunnel junctions.

We locally investigate the electronic transport through individual tunnel junctions containing a 10 nm thin film of vanadium dioxide (VO2) across its thermally induced phase transition. The insulator-to-metal phase transition in the VO2 film collapses the Hubbard gap (experimentally determined to be 0.4 ± 0.07 V), leading to several orders of magnitude change in tunnel conductance. We quantitatively evaluate underlying transport mechanisms via theoretical quantum mechanical transport calculations which show excellent agreement with the experimental results.

Atomically thin heterostructures based on single-layer tungsten diselenide and graphene.

Heterogeneous engineering of two-dimensional layered materials, including metallic graphene and semiconducting transition metal dichalcogenides, presents an exciting opportunity to produce highly tunable electronic and optoelectronic systems. In order to engineer pristine layers and their interfaces, epitaxial growth of such heterostructures is required. We report the direct growth of crystalline, monolayer tungsten diselenide (WSe2) on epitaxial graphene (EG) grown from silicon carbide. Raman spectroscopy, photoluminescence, and scanning tunneling microscopy confirm high-quality WSe2 monolayers, whereas transmission electron microscopy shows an atomically sharp interface, and low energy electron diffraction confirms near perfect orientation between WSe2 and EG. Vertical transport measurements across the WSe2/EG heterostructure provides evidence that an additional barrier to carrier transport beyond the expected WSe2/EG band offset exists due to the interlayer gap, which is supported by theoretical local density of states (LDOS) calculations using self-consistent density functional theory (DFT) and nonequilibrium Green's function (NEGF).

In-Operando Spatiotemporal Imaging of Coupled Film-Substrate Elastodynamics During an Insulator-to-Metal Transition.

The drive toward non-von Neumann device architectures has led to an intense focus on insulator-to-metal (IMT) and the converse metal-to-insulator (MIT) transitions. Studies of electric field-driven IMT in the prototypical VO2 thin-film channel devices are largely focused on the electrical and elastic responses of the films, but the response of the corresponding TiO2 substrate is often overlooked, since it is nominally expected to be electrically passive and elastically rigid. Here, in-operando spatiotemporal imaging of the coupled elastodynamics using X-ray diffraction microscopy of a VO2 film channel device on TiO2 substrate reveals two new surprises. First, the film channel bulges during the IMT, the opposite of the expected shrinking in the film undergoing IMT. Second, a microns thick proximal layer in the substrate also coherently bulges accompanying the IMT in the film, which is completely unexpected. Phase-field simulations of coupled IMT, oxygen vacancy electronic dynamics, and electronic carrier diffusion incorporating thermal and strain effects suggest that the observed elastodynamics can be explained by the known naturally occurring oxygen vacancies that rapidly ionize (and deionize) in concert with the IMT (MIT). Fast electrical-triggering of the IMT via ionizing defects and an active "IMT-like" substrate layer are critical aspects to consider in device applications.

Enhanced transport and transistor performance with oxide seeded high-κ gate dielectrics on wafer-scale epitaxial graphene.

We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer deposition that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Additionally, high-κ seeded dielectrics are shown to produce superior transistor performance relative to low-κ seeded dielectrics and the presence of heterogeneous seed/overlayer structures is found to be detrimental to transistor performance, reducing effective mobility by 30-40%. The direct deposition of high-purity oxide seed represents the first robust method for the deposition of uniform atomic layer deposited dielectrics on epitaxial graphene that improves carrier transport.

Interlayer Engineering of Band Gap and Hole Mobility in p-Type Oxide SnO.

The development of high-performance p-type oxides with wide band gap and high hole mobility is critical for the application of oxide semiconductors in back-end-of-line (BEOL) complementary metal-oxide-semiconductor (CMOS) devices. SnO has been intensively studied as a high-mobility p-type oxide due to its low effective hole mass resulting from the hybridized O-2p/Sn-5s orbital character at the valence band edge. However, SnO has a very small band gap (∼0.7 eV) for practical p-type oxide devices. In this work, we report an engineering method to enhance the band gap and hole mobility in SnO. It is found that both the band gap and the hole mobility of a layer-structured SnO increase with the interlayer stacking spacing change. By exploiting this unique electronic structure feature, we propose expanding the interlayer spacing by interlayer intercalation to engineer the band gap and p-type mobility in SnO. Small molecules like NH3 and CH4 are shown to be capable of expanding the interlayer spacing and of increasing the band gap and hole mobility in SnO and thus could potentially serve as the interlayer intercalants. The results provide a viable way for the experimental realization of wide-band-gap and high hole-mobility p-type SnO for BEOL vertical CMOS device applications.

Toward attojoule switching energy in logic transistors.

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling-the decrease of component sizes-with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.

Neural sampling machine with stochastic synapse allows brain-like learning and inference.

Many real-world mission-critical applications require continual online learning from noisy data and real-time decision making with a defined confidence level. Brain-inspired probabilistic models of neural network can explicitly handle the uncertainty in data and allow adaptive learning on the fly. However, their implementation in a compact, low-power hardware remains a challenge. In this work, we introduce a novel hardware fabric that can implement a new class of stochastic neural network called Neural Sampling Machine (NSM) by exploiting the stochasticity in the synaptic connections for approximate Bayesian inference. We experimentally demonstrate an in silico hybrid stochastic synapse by pairing a ferroelectric field-effect transistor (FeFET)-based analog weight cell with a two-terminal stochastic selector element. We show that the stochastic switching characteristic of the selector between the insulator and the metallic states resembles the multiplicative synaptic noise of the NSM. We perform network-level simulations to highlight the salient features offered by the stochastic NSM such as performing autonomous weight normalization for continual online learning and Bayesian inferencing. We show that the stochastic NSM can not only perform highly accurate image classification with 98.25% accuracy on standard MNIST dataset, but also estimate the uncertainty in prediction (measured in terms of the entropy of prediction) when the digits of the MNIST dataset are rotated. Building such a probabilistic hardware platform that can support neuroscience inspired models can enhance the learning and inference capability of the current artificial intelligence (AI).

Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors.

Tunnel field-effect transistors were fabricated from axially doped silicon nanowire p-n junctions grown via the vapor-liquid-solid method. Following dry thermal oxidation to form a gate dielectric shell, the nanowires have a p-n-n(+) doping profile with an abrupt n-n(+) junction, which was revealed by scanning capacitance microscopy. The lightly doped n-segment can be inverted to p(+) by modulating the top gate bias, thus forming an abrupt gated p(+)-n(+) junction. A band-to-band tunneling current flows through the electrostatically doped p(+)-n(+) junction when it is reverse biased. Current-voltage measurements performed from 375 down to 4.2 K show two different regimes of tunneling current at high and low temperatures, indicating that there are both direct band-to-band and trap-assisted tunneling paths.

Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis.

Resistance switching in metal-insulator-metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility. In this work, we have addressed these issues by demonstrating the use of ultraporous dielectrics as a pathway for high-performance resistive memory devices. Using a modified atomic layer deposition based technique known as sequential infiltration synthesis, which was developed originally for improving polymer properties such as enhanced etch resistance of electron-beam resists and for the creation of films for filtration and oleophilic applications, we are able to create ∼15 nm thick ultraporous (pore size ∼5 nm) oxide dielectrics with up to 73% porosity as the medium for filament formation. We show, using the Ag/Al2O3 system, that the ultraporous films result in ultrahigh on/off ratio (>109) at ultralow switching voltages (∼±600 mV) that are 10× smaller than those for the bulk case. In addition, the devices demonstrate fast switching, pulsed endurance up to 1 million cycles. and high temperature (125 °C) retention up to 104 s, making this approach highly promising for large-scale neuromorphic and memory applications. Additionally, this synthesis methodology provides a compatible, inexpensive route that is scalable and compatible with existing semiconductor nanofabrication methods and materials.

Stochastic Resonance in Insulator-Metal-Transition Systems.

Stochastic resonance (SR) is an ingenious phenomenon observed in nature and in biological systems but has seen very few practical applications in engineering. It has been observed and analyzed in widely different natural phenomenon including in bio-organisms (e.g. Mechanoreceptor of crayfish) and in environmental sciences (e.g. the periodic occurrence of ice ages). The main idea behind SR seems quite unorthodox - it proposes that noise, that is intrinsically present in a system or is extrinsically added, can help enhance the signal power at the output, in a desired frequency range. Despite its promise and ubiquitous presence in nature, SR has not been successively harnessed in engineering applications. In this work, we demonstrate both experimentally as well as theoretically how the intrinsic threshold noise of an insulator-metal-transition (IMT) material can enable SR. We borrow inspiration from natural systems which use SR to detect and amplify low-amplitude signals, to demonstrate how a simple electrical circuit which uses an IMT device can exploit SR in engineering applications. We explore two such applications: one of them utilizes noise to correctly transmit signals corresponding to different vowel sounds akin to auditory nerves, without amplifying the amplitude of the input audio sound. This finds applications in cochlear implants where ultra-low power consumption is a primary requirement. The second application leverages the frequency response of SR, where the loss of resonance at out-of-band frequencies is used. We demonstrate how to provide frequency selectivity by tuning an extrinsically added noise to the system.

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges.

The two possible pathways toward artificial intelligence (AI)-(i) neuroscience-oriented neuromorphic computing [like spiking neural network (SNN)] and (ii) computer science driven machine learning (like deep learning) differ widely in their fundamental formalism and coding schemes (Pei et al., 2019). Deviating from traditional deep learning approach of relying on neuronal models with static nonlinearities, SNNs attempt to capture brain-like features like computation using spikes. This holds the promise of improving the energy efficiency of the computing platforms. In order to achieve a much higher areal and energy efficiency compared to today's hardware implementation of SNN, we need to go beyond the traditional route of relying on CMOS-based digital or mixed-signal neuronal circuits and segregation of computation and memory under the von Neumann architecture. Recently, ferroelectric field-effect transistors (FeFETs) are being explored as a promising alternative for building neuromorphic hardware by utilizing their non-volatile nature and rich polarization switching dynamics. In this work, we propose an all FeFET-based SNN hardware that allows low-power spike-based information processing and co-localized memory and computing (a.k.a. in-memory computing). We experimentally demonstrate the essential neuronal and synaptic dynamics in a 28 nm high-K metal gate FeFET technology. Furthermore, drawing inspiration from the traditional machine learning approach of optimizing a cost function to adjust the synaptic weights, we implement a surrogate gradient (SG) learning algorithm on our SNN platform that allows us to perform supervised learning on MNIST dataset. As such, we provide a pathway toward building energy-efficient neuromorphic hardware that can support traditional machine learning algorithms. Finally, we undertake synergistic device-algorithm co-design by accounting for the impacts of device-level variation (stochasticity) and limited bit precision of on-chip synaptic weights (available analog states) on the classification accuracy.

Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating.

In this work, we demonstrate high-performance indium-tin-oxide (ITO) transistors with a channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. An on-current of 0.243 A/mm is achieved on submicron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ω·mm and a low contact resistivity of 1.1 × 10-7 Ω·cm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin-film transistors, including large-area wafer-size nanometer thin-film formation, low contact resistance and contact resistivity, an atomic thin channel being immune to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line complementary metal-oxide-semiconductor application.

Stabilizing the commensurate charge-density wave in 1T-tantalum disulfide at higher temperatures via potassium intercalation.

The 1T phase of tantalum disulfide (1T-TaS2) possesses a variety of charge-density-wave (CDW) orders, and as a result, it attracts an increasing amount of academic and technological interest. Researchers have devoted tremendous efforts towards understanding the impacts of doping, alloying, intercalation or other triggering agents on its charge density wave orders. In this work, we demonstrate that incorporating potassium chloride (KCl) during chemical vapor deposition (CVD) of TaS2 can control the phase (1T, 2H or metal nanowires) via the intercalation of potassium ions (K+) between TaS2 layers. Finally, we demonstrate that K+ not only impacts the structure during synthesis but also strongly impacts the CDW phase transition as a function of temperature, increasing the nearly commensurate (NCCDW) to commensurate (CCDW) transition to just below room temperature.