Nanotube Alignment Mechanism in Floating Evaporative Self-Assembly.

The challenge of assembling semiconducting single-wall carbon nanotubes (s-SWCNTs) into densely packed, aligned arrays has limited the scalability and practicality of high-performance nanotube-based electronics technologies. The aligned deposition of s-SWCNTs via floating evaporative self-assembly (FESA) has promise for overcoming this challenge; however, the mechanisms behind FESA need to be elucidated before the technique can be improved and scaled. Here, we gain a deeper understanding of the FESA process by studying a stationary analogue of FESA and optically tracking the dynamics of the organic ink/water/substrate and ink/air/substrate interfaces during the typical FESA process. We observe that the ink/water interface serves to collect and confine the s-SWCNTs before alignment and that the deposition of aligned bands of s-SWCNTs occurs at the ink/water/substrate contact line during the depinning of both the ink/air/substrate and ink/water/substrate contact lines. We also demonstrate improved control over the interband spacing, bandwidth, and packing density of FESA-aligned s-SWCNT arrays. The substrate lift rate (5-15 mm min-1) is used to tailor the interband spacing from 90 to 280 µm while maintaining a constant aligned s-SWCNT bandwidth of 50 µm. Varying the s-SWCNT ink concentration (0.75-10 µg mL-1) allows the control of the bandwidth from 2.5 to 45 µm. A steep increase in packing density is observed from 11 s-SWCNTs µm-1 at 0.75 µg mL-1 to 20 s-SWCNTs µm-1 at 2 µg mL-1, with a saturated packing density of ∼24 s-SWCNTs µm-1. We also demonstrate the scaling of FESA to align s-SWCNTs on a 2.5 × 2.5 cm2 scale while preserving high-quality alignment on the nanometer scale. These findings help realize the scalable fabrication of well-aligned s-SWCNT arrays to serve as large-area platforms for next-generation semiconductor electronics.

Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs.

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G 0 = 4e (2)/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G 0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs µm(-1), fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G 0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS µm(-1), which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 µA µm(-1) and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.