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1.
J Am Chem Soc ; 142(1): 134-145, 2020 Jan 08.
Artigo em Inglês | MEDLINE | ID: mdl-31779305

RESUMO

Silicon germanium (SiGe) is a multifunctional material considered for quantum computing, neuromorphic devices, and CMOS transistors. However, implementation of SiGe in nanoscale electronic devices necessitates suppression of surface states dominating the electronic properties. The absence of a stable and passive surface oxide for SiGe results in the formation of charge traps at the SiGe-oxide interface induced by GeOx. In an ideal ALD process in which oxide is grown layer by layer, the GeOx formation should be prevented with selective surface oxidation (i.e., formation of an SiOx interface) by controlling the oxidant dose in the first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during the entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in nonideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (Dit) across the band gap by nearly 1 order of magnitude in Al2O3 (<6 × 1010 cm-2) and in HfO2 (<3.9 × 1011 cm-2) by forming a SiOx-rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeOx formation and consequent desorption from the SiGe with ozone insertion during the ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at the SiGe-oxide interface is demonstrated, which is engineering of diffusion species in the ALD process due to facile diffusion of reactant species in nonideal ALD.

2.
ACS Appl Mater Interfaces ; 11(16): 15111-15121, 2019 Apr 24.
Artigo em Inglês | MEDLINE | ID: mdl-30938163

RESUMO

Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x-rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al2O3 in contrast to HfO2 on SiGe; however, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al2O3/SiGe is investigated using atomic layer deposited (ALD) Al2O3 insertion into or on top of ALD HfO2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al2O3/SiGe and HfO2/SiGe interfaces with the insertion of Al2O3 into or on top of the HfO2 oxide. The data is consistent with the Al2O3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.

3.
ACS Sens ; 3(3): 640-647, 2018 03 23.
Artigo em Inglês | MEDLINE | ID: mdl-29400061

RESUMO

The effect of thermal treatments, on the benzene vapor sensitivity of polyethylene (co-)vinylacetate (PEVA)/graphene nanocomposite threads, used as chemiresistive sensors, was investigated using DC resistance measurements, differential scanning calorimetry (DSC), and scanning electron microscopy (SEM). These flexible threads are being developed as low-cost, easy-to-measure chemical sensors that can be incorporated into smart clothing or disposable sensing patches. Chemiresistive threads were solution-cast or extruded from PEVA and <10% graphene nanoplatelets (by mass) in toluene. Threads were annealed at various temperatures and showed up to 2 orders of magnitude decrease in resistance with successive anneals. Threads heated to ≥80 °C showed improved limits of detection, resulting from improved signal-noise, when exposed to benzene vapor in dry air. In addition, annealing increased the speed of response and recovery upon exposure to and removal of benzene vapor. DSC results showed that the presence of graphene raises the freezing point, and may allow greater crystallinity, in the nanocomposite after annealing. SEM images confirm increased surface roughness/area, which may account for the increase response speed after annealing. Benzene vapor detection at 5 ppm is demonstrated with limits of detection estimated to be as low as 1.5 ppm, reflecting an order of magnitude improvement over unannealed threads.


Assuntos
Benzeno/análise , Grafite/química , Nanocompostos/química , Polivinil/química , Temperatura , Tamanho da Partícula , Propriedades de Superfície , Volatilização
4.
ACS Appl Mater Interfaces ; 10(36): 30794-30802, 2018 Sep 12.
Artigo em Inglês | MEDLINE | ID: mdl-30073827

RESUMO

The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO x. This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO x at the interface; the remaining ultrathin interlayer is consistent with a SiO x-rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO x-rich surface layer can produce an electrically passivated HfO2/SiGe interface. To form this SiO x-rich interlayer, metal gate stack designs including Al/HfO2/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO2-Al2O3) were investigated. As compared to the control Ni-gated devices, those with Al/HfO2/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO x-rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO2 by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.

5.
J Phys Chem B ; 110(1): 361-6, 2006 Jan 12.
Artigo em Inglês | MEDLINE | ID: mdl-16471543

RESUMO

The electrical properties of 50 nm thick metallophthalocyanine films, prepared by organic molecular beam epitaxy (OMBE) on interdigitated electrodes, were studied with DC current-voltage measurements and impedance spectroscopy. The transition from Ohmic behavior at low voltages to space-charge-limited conductivity (SCLC) at higher voltages depends on the metal electrode (Pt, Pd, and Au), but does not correlate with the work function of the electrode. Impedance spectroscopy studies show the coexistence of low- and high-frequency traps in the thin film devices, and the contribution of low-frequency traps associated with Ohmic behavior diminishes at higher bias. Although device resistances are strongly influenced by the electrode material, and vary by a factor of over 300, the relative chemical sensor responses on exposure to dimethyl methylphosphonate (DMMP), methanol, water, or toluene vapors are similar for CoPc on Pt, Pd, and Au electrodes when these devices are operated in the SCLC regime at room temperature. When the devices are operated at voltages where the low-frequency interfacial traps are filled, the sensor response to analyte becomes uniform and reliable regardless of the specific interfacial electrode contact.


Assuntos
Condutividade Elétrica , Indóis/química , Compostos Organometálicos/química , Eletrodos , Membranas Artificiais , Silício/química , Dióxido de Silício/química , Propriedades de Superfície
6.
ACS Appl Mater Interfaces ; 8(24): 14994-9, 2016 Jun 22.
Artigo em Inglês | MEDLINE | ID: mdl-27248803

RESUMO

Cryogenic focused ion beam (Cryo-FIB) milling at near-grazing angles is employed to fabricate cross-sections on thin Cu(In,Ga)Se2 with >8x expansion in thickness. Kelvin probe force microscopy (KPFM) on sloped cross sections showed reduction in grain boundaries potential deeper into the film. Cryo Fib-KPFM enabled the first determination of the electronic structure of the Mo/CIGSe back contact, where a sub 100 nm thick MoSey assists hole extraction due to 45 meV higher work function. This demonstrates that CryoFIB-KPFM combination can reveal new targets of opportunity for improvement in thin-films photovoltaics such as high-work-function contacts to facilitate hole extraction through the back interface of CIGS.

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