A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 µW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.

A Spatially Diverse 2TX-3RX Galvanic-Coupled Transdural Telemetry for Tether-Less Distributed Brain-Computer Interfaces.

A near-field galvanic coupled transdural telemetry ASICs for intracortical brain-computer interfaces is presented. The proposed design features a two channels transmitter and three channels receiver (2TX-3RX) topology, which introduces spatial diversity to effectively mitigate misalignments (both lateral and rotational) between the brain and the skull and recovers the path loss by 13 dB when the RX is in the worst-case blind spot. This spatial diversity also allows the presented telemetry to support the spatial division multiplexing required for a high-capacity multi-implant distributed network. It achieves a signal-to-interference ratio of 12 dB, even with the adjacent interference node placed only 8 mm away from the desired link. While consuming only 0.33 mW for each channel, the presented RX achieves a wide bandwidth of 360 MHz and a low input referred noise of 13.21 nV/√Hz. The presented telemetry achieves a 270 Mbps data rate with a BER<10-6 and an energy efficiency of 3.4 pJ/b and 3.7 pJ/b, respectively. The core footprint of the TX and RX modules is only 100 and 52 mm2, respectively, minimizing the invasiveness of the surgery. The proposed transdural telemetry system has been characterized ex-vivo with a 7-mm thick porcine tissue.

An Event-based Neural Compressive Telemetry with >11× Loss-less Data Reduction for High-bandwidth Intracortical Brain Computer Interfaces.

Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts of data to be transferred. This requires power-hungry data serialization and telemetry, leading to potential tissue damage risks. To address this challenge, this paper introduces an event-based neural compressive telemetry (NCT) consisting of 8 channel-rotating Δ-ADCs, an event-driven serializer supporting a proposed ternary address event representation protocol, and an event-based LVDS driver. Leveraging a high sparsity of extracellular spikes and high spatial correlation of the high-density recordings, the proposed NCT achieves a compression ratio of >11.4×, while consumes only 1 µW per channel, which is 127× more efficient than state of the art. The NCT well preserves the spike waveform fidelity, and has a low normalized RMS error <23% even with a spike amplitude down to only 31 µV.