High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Effect of heat shield locations on rework-induced thermal management in ball grid array solder joint.

This study investigated the effectiveness of heat shield placement locations during the rework process to avoid thermal and mechanical damage to adjacent ball grid array components and their solder joints on double-sided printed circuit board assembly. Three types of heat shield placement locations were used: sample X, individual heat shield placement on adjacent components of the rework location; sample Y, a U-shaped, and sample Z, a square-shaped heat shield placed respectively at the heat source location. The dye and pull test results, infrared thermography, and temperature measurements were analysed to understand the relationship between the location of the heat shield and solder joint damage during rework. Heat shield placement at the heat source location on the reworked component can reduce the peak temperatures on the adjacent rework component locations by up to 8.18%. The peak temperatures of the centre and corner of the BGA component can be maintained below 195 °C and 210 °C, respectively to improve the adjacent rework component locations' solder joint quality by reducing solder joint damage by more than 50% solder cracks. This is useful for thermal management during rework involving high-density ball grid array component placements on double-sided printed circuit board assembly.

Effect of geometric parameters on the performance of p-type junctionless lateral gate transistors.

This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed.