In situ observations of gas phase dynamics during graphene growth using solid-state carbon sources.

A single-layer graphene has been uniformly grown on a Cu surface at elevated temperatures by thermal processing of a poly(methyl methacrylate) (PMMA) film in a rapid thermal annealing (RTA) system under vacuum. The detailed chemistry of the transition from solid-state carbon to graphene on the catalytic Cu surface was investigated by performing in situ residual gas analysis while PMMA/Cu-foil samples were being heated, in conjunction with interrupted growth studies to reconstruct ex situ the heating process. The data clearly show that the formation of graphene occurs by vaporizing hydrocarbon molecules from PMMA, such as methane and/or methyl radicals, which act as precursors, rather than by the direct graphitization of solid-state carbon. We also found that the temperature for vaporizing hydrocarbon molecules from PMMA and the length of time the gaseous hydrocarbon atmosphere is maintained, which are dependent on both the heating temperature profile and the amount of a solid carbon feedstock, are the dominant factors that determine the crystalline quality of the resulting graphene film. Under optimal growth conditions, the PMMA-derived graphene was found to have a carrier (hole) mobility as high as ∼2700 cm(2) V(-1) s(-1) at room temperature, which is superior to common graphene converted from solid carbon.

Fabrication of p-type 2D single-crystalline transistor arrays with Fermi-level-tuned van der Waals semimetal electrodes.

High-performance p-type two-dimensional (2D) transistors are fundamental for 2D nanoelectronics. However, the lack of a reliable method for creating high-quality, large-scale p-type 2D semiconductors and a suitable metallization process represents important challenges that need to be addressed for future developments of the field. Here, we report the fabrication of scalable p-type 2D single-crystalline 2H-MoTe2 transistor arrays with Fermi-level-tuned 1T'-phase semimetal contact electrodes. By transforming polycrystalline 1T'-MoTe2 to 2H polymorph via abnormal grain growth, we fabricated 4-inch 2H-MoTe2 wafers with ultra-large single-crystalline domains and spatially-controlled single-crystalline arrays at a low temperature (~500 °C). Furthermore, we demonstrate on-chip transistors by lithographic patterning and layer-by-layer integration of 1T' semimetals and 2H semiconductors. Work function modulation of 1T'-MoTe2 electrodes was achieved by depositing 3D metal (Au) pads, resulting in minimal contact resistance (~0.7 kΩ·µm) and near-zero Schottky barrier height (~14 meV) of the junction interface, and leading to high on-state current (~7.8 µA/µm) and on/off current ratio (~105) in the 2H-MoTe2 transistors.

One-step graphene coating of heteroepitaxial GaN films.

Today, state-of-the-art III-Ns technology has been focused on the growth of c-plane nitrides by metal-organic chemical vapor deposition (MOCVD) using a conventional two-step growth process. Here we show that the use of graphene as a coating layer allows the one-step growth of heteroepitaxial GaN films on sapphire in a MOCVD reactor, simplifying the GaN growth process. It is found that the graphene coating improves the wetting between GaN and sapphire, and, with as little as ~0.6 nm of graphene coating, the overgrown GaN layer on sapphire becomes continuous and flat. With increasing thickness of the graphene coating, the structural and optical properties of one-step grown GaN films gradually transition towards those of GaN films grown by a conventional two-step growth method. The InGaN/GaN multiple quantum well structure grown on a GaN/graphene/sapphire heterosystem shows a high internal quantum efficiency, allowing the use of one-step grown GaN films as 'pseudo-substrates' in optoelectronic devices. The introduction of graphene as a coating layer provides an atomic playground for metal adatoms and simplifies the III-Ns growth process, making it potentially very useful as a means to grow other heteroepitaxial films on arbitrary substrates with lattice and thermal mismatch.

Synthesis of high quality 2D carbide MXene flakes using a highly purified MAX precursor for ink applications.

The practical application of 2D MXenes in electronic and energy fields has been hindered by the severe variation in the quality of MXene products depending on the parent MAX phases, manufacturing techniques, and preparation parameters. In particular, their synthesis has been impeded by the lack of studies reporting the synthesis of high-quality parent MAX phases. In addition, controllable and uniform deposition of 2D MXenes on various large-scale substrates is urgently required to use them practically. Herein, a method of pelletizing raw materials could synthesize a stoichiometric Ti3AlC2 MAX phase with high yield and processability, and fewer impurities. The Ti3AlC2 could be exfoliated into 1-2-atom-thick 2D Ti3C2T x flakes, and their applicability was confirmed by the deposition and additional alignment of the 2D flakes with tunable thickness and electrical properties. Moreover, a practical MXene ink was fabricated with rheological characterization. MXene ink exhibited much better thickness uniformity while retaining excellent electrical performances (e.g., sheet resistance, electromagnetic interference shielding ability) as those of a film produced by vacuum filtration. The direct functional integration of MXenes on various substrates is expected to initiate new and unexpected MXene-based applications.

Recent Developments in Controlled Vapor-Phase Growth of 2D Group 6 Transition Metal Dichalcogenides.

An overview of recent developments in controlled vapor-phase growth of 2D transition metal dichalcogenide (2D TMD) films is presented. Investigations of thin-film formation mechanisms and strategies for realizing 2D TMD films with less-defective large domains are of central importance because single-crystal-like 2D TMDs exhibit the most beneficial electronic and optoelectronic properties. The focus is on the role of the various growth parameters, including strategies for efficiently delivering the precursors, the selection and preparation of the substrate surface as a growth assistant, and the introduction of growth promoters (e.g., organic molecules and alkali metal halides) to facilitate the layered growth of (Mo, W)(S, Se, Te)2 atomic crystals on inert substrates. Critical factors governing the thermodynamic and kinetic factors related to chemical reaction pathways and the growth mechanism are reviewed. With modification of classical nucleation theory, strategies for designing and growing various vertical/lateral TMD-based heterostructures are discussed. Then, several pioneering techniques for facile observation of structural defects in TMDs, which substantially degrade the properties of macroscale TMDs, are introduced. Technical challenges to be overcome and future research directions in the vapor-phase growth of 2D TMDs for heterojunction devices are discussed in light of recent advances in the field.

Electrically Robust Single-Crystalline WTe2 Nanobelts for Nanoscale Electrical Interconnects.

As the elements of integrated circuits are downsized to the nanoscale, the current Cu-based interconnects are facing limitations due to increased resistivity and decreased current-carrying capacity because of scaling. Here, the bottom-up synthesis of single-crystalline WTe2 nanobelts and low- and high-field electrical characterization of nanoscale interconnect test structures in various ambient conditions are reported. Unlike exfoliated flakes obtained by the top-down approach, the bottom-up growth mode of WTe2 nanobelts allows systemic characterization of the electrical properties of WTe2 single crystals as a function of channel dimensions. Using a 1D heat transport model and a power law, it is determined that the breakdown of WTe2 devices under vacuum and with AlO x capping layer follows an ideal pattern for Joule heating, far from edge scattering. High-field electrical measurements and self-heating modeling demonstrate that the WTe2 nanobelts have a breakdown current density approaching ≈100 MA cm-2, remarkably higher than those of conventional metals and other transition-metal chalcogenides, and sustain the highest electrical power per channel length (≈16.4 W cm-1) among the interconnect candidates. The results suggest superior robustness of WTe2 against high-bias sweep and its possible applicability in future nanoelectronics.

Unraveling the Water Impermeability Discrepancy in CVD-Grown Graphene.

Graphene has recently attracted particular interest as a flexible barrier film preventing permeation of gases and moistures. However, it has been proved to be exceptionally challenging to develop large-scale graphene films with little oxygen and moisture permeation suitable for industrial uses, mainly due to the presence of nanometer-sized defects of obscure origins. Here, the origins of water permeable routes on graphene-coated Cu foils are investigated by observing the micrometer-sized rusts in the underlying Cu substrates, and a site-selective passivation method of the nanometer-sized routes is devised. It is revealed that nanometer-sized holes or cracks are primarily concentrated on graphene wrinkles rather than on other structural imperfections, resulting in severe degradation of its water impermeability. They are found to be predominantly induced by the delamination of graphene bound to Cu as a release of thermal stress during the cooling stage after graphene growth, especially at the intersection of the Cu step edges and wrinkles owing to their higher adhesion energy. Furthermore, the investigated routes are site-selectively passivated by an electron-beam-induced amorphous carbon layer, thus a substantial improvement in water impermeability is achieved. This approach is likely to be extended for offering novel barrier properties in flexible films based on graphene and on other atomic crystals.

The impact of substrate surface defects on the properties of two-dimensional van der Waals heterostructures.

The recent emergence of vertically stacked van der Waals (vdW) heterostructures provides new opportunities for these materials to be employed in a wide range of novel applications. Understanding the interlayer coupling in the stacking geometries of the heterostructures and its effect on the resultant material properties is particularly important for obtaining materials with desirable properties. Here, we report that the atomic bonding between stacked layers and thereby the interlayer properties of the vdW heterostructures can be well tuned by the substrate surface defects using WS2 flakes directly grown on graphene. We show that the defects of graphene have no significant effect on the crystal structure or the quality of the grown WS2 flakes; however, they have a strong influence on the interlayer interactions between stacked layers, thus affecting the layer deformability, thermal stability, and physical and electrical properties. Our experimental and computational investigations also reveal that WS2 flakes grown on graphene defects form covalent bonds with the underlying graphene via W atomic bridges (i.e., formation of larger overlapping hybrid orbitals), enabling these flakes to exhibit different intrinsic properties, such as higher conductivity and improved contact characteristics than heterostructures that have vdW interactions with graphene. This result emphasizes the importance of understanding the interlayer coupling in the stacking geometries and its correlation effect for designing desirable properties.

Single-Crystalline Nanobelts Composed of Transition Metal Ditellurides.

Following the celebrated discovery of graphene, considerable attention has been directed toward the rich spectrum of properties offered by van der Waals crystals. However, studies have been largely limited to their 2D properties due to lack of 1D structures. Here, the growth of high-yield, single-crystalline 1D nanobelts composed of transition metal ditellurides at low temperatures (T ≤ 500 °C) and in short reaction times (t ≤ 10 min) via the use of tellurium-rich eutectic metal alloys is reported. The synthesized semimetallic 1D products are highly pure, stoichiometric, structurally uniform, and free of defects, resulting in high electrical performances. Furthermore, complete compositional tuning of the ternary ditelluride nanobelts is achieved with suppressed phase separation, applicable to the creation of unprecedented low-dimensional materials/devices. This approach may inspire new growth/fabrication strategies of 1D layered nanostructures, which may offer unique properties that are not available in other materials.

Oxidation behavior of graphene-coated copper at intrinsic graphene defects of different origins.

The development of ultrathin barrier films is vital to the advanced semiconductor industry. Graphene appears to hold promise as a protective coating; however, the polycrystalline and defective nature of engineered graphene hinders its practical applications. Here, we investigate the oxidation behavior of graphene-coated Cu foils at intrinsic graphene defects of different origins. Macro-scale information regarding the spatial distribution and oxidation resistance of various graphene defects is readily obtained using optical and electron microscopies after the hot-plate annealing. The controlled oxidation experiments reveal that the degree of structural deficiency is strongly dependent on the origins of the structural defects, the crystallographic orientations of the underlying Cu grains, the growth conditions of graphene, and the kinetics of the graphene growth. The obtained experimental and theoretical results show that oxygen radicals, decomposed from water molecules in ambient air, are effectively inverted at Stone-Wales defects into the graphene/Cu interface with the assistance of facilitators.

Growth of wrinkle-free graphene on texture-controlled platinum films and thermal-assisted transfer of large-scale patterned graphene.

Growth of large-scale patterned, wrinkle-free graphene and the gentle transfer technique without further damage are most important requirements for the practical use of graphene. Here we report the growth of wrinkle-free, strictly uniform monolayer graphene films by chemical vapor deposition on a platinum (Pt) substrate with texture-controlled giant grains and the thermal-assisted transfer of large-scale patterned graphene onto arbitrary substrates. The designed Pt surfaces with limited numbers of grain boundaries and improved surface perfectness as well as small thermal expansion coefficient difference to graphene provide a venue for uniform growth of monolayer graphene with wrinkle-free characteristic. The thermal-assisted transfer technique allows the complete transfer of large-scale patterned graphene films onto arbitrary substrates without any ripples, tears, or folds. The transferred graphene shows high crystalline quality with an average carrier mobility of ∼ 5500 cm(2) V(-1) s(-1) at room temperature. Furthermore, this transfer technique shows a high tolerance to variations in types and morphologies of underlying substrates.

Monolithic graphene oxide sheets with controllable composition.

Graphene oxide potentially has multiple applications and is typically prepared by solution-based chemical means. To date, the synthesis of a monolithic form of graphene oxide that is crucial to the precision assembly of graphene-based devices has not been achieved. Here we report the physical approach to produce monolithic graphene oxide sheets on copper foil using solid carbon, with tunable oxygen-to-carbon composition. Experimental and theoretical studies show that the copper foil provides an effective pathway for carbon diffusion, trapping the oxygen species dissolved in copper and enabling the formation of monolithic graphene oxide sheets. Unlike chemically derived graphene oxide, the as-synthesized graphene oxide sheets are electrically active, and the oxygen-to-carbon composition can be tuned during the synthesis process. As a result, the resulting graphene oxide sheets exhibit tunable bandgap energy and electronic properties. Our solution-free, physical approach may provide a path to a new class of monolithic, two-dimensional chemically modified carbon sheets.

Facile synthesis of few-layer graphene with a controllable thickness using rapid thermal annealing.

Few-layer graphene films with a controllable thickness were grown on a nickel surface by rapid thermal annealing (RTA) under vacuum. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2-3 nm) carbon- and oxygen-containing compounds on a nickel surface; thus, the high-temperature annealing of the nickel samples without the introduction of intentional carbon-containing precursors results in the formation of graphene films. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time, and the resulting films have a limited thickness (<2 nm), even for an extended RTA time. The transferred films have a low sheet resistance of ~0.9 ± 0.4 kΩ/sq, with ~94% ± 2% optical transparency, making them useful for applications as flexible transparent conductors.

Near room-temperature synthesis of transfer-free graphene films.

Large-area graphene films are best synthesized via chemical vapour and/or solid deposition methods at elevated temperatures (~1,000 °C) on polycrystalline metal surfaces and later transferred onto other substrates for device applications. Here we report a new method for the synthesis of graphene films directly on SiO(2)/Si substrates, even plastics and glass at close to room temperature (25-160 °C). In contrast to other approaches, where graphene is deposited on top of a metal substrate, our method invokes diffusion of carbon through a diffusion couple made up of carbon-nickel/substrate to form graphene underneath the nickel film at the nickel-substrate interface. The resulting graphene layers exhibit tunable structural and optoelectronic properties by nickel grain boundary engineering and show micrometre-sized grains on SiO(2) surfaces and nanometre-sized grains on plastic and glass surfaces. The ability to synthesize graphene directly on non-conducting substrates at low temperatures opens up new possibilities for the fabrication of multiple nanoelectronic devices.