Two-Dimensional MXene Synapse for Brain-Inspired Neuromorphic Computing.

MXenes, an emerging class of two-dimensional (2D) transition metal carbides and nitrides, have attracted wide attention because of their fascinating properties required in functional electronics. Here, an atomic-switch-type artificial synapse fabricated on Ti3 C2 Tx MXene nanosheets with lots of surface functional groups, which successfully mimics the dynamics of biological synapses, is reported. Through in-depth analysis by X-ray photoelectron spectroscopy, transmission electron microscopy, and energy dispersive X-ray spectroscopy, it is found that the synaptic dynamics originated from the gradual formation and annihilation of the conductive metallic filaments on the MXene surface with distributed functional groups. Subsequently, via training and inference tasks using a convolutional neural network for the Canadian-Institute-For-Advanced-Research-10 dataset, the applicability of the artificial MXene synapse to hardware neural networks is demonstrated.

Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing.

Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology.

High-Efficiency WSe2 Photovoltaic Devices with Electron-Selective Contacts.

A rapid surge in global energy consumption has led to a greater demand for renewable energy to overcome energy resource limitations and environmental problems. Recently, a number of van der Waals materials have been highlighted as efficient absorbers for very thin and highly efficient photovoltaic (PV) devices. Despite the predicted potential, achieving power conversion efficiencies (PCEs) above 5% in PV devices based on van der Waals materials has been challenging. Here, we demonstrate a vertical WSe2 PV device with a high PCE of 5.44% under one-sun AM1.5G illumination. We reveal the multifunctional nature of a tungsten oxide layer, which promotes a stronger internal electric field by overcoming limitations imposed by the Fermi-level pinning at WSe2 interfaces and acts as an electron-selective contact in combination with monolayer graphene. Together with the developed bottom contact scheme, this simple yet effective contact engineering method improves the PCE by more than five times.

A Van Der Waals Reconfigurable Multi-Valued Logic Device and Circuit Based on Tunable Negative-Differential-Resistance Phenomenon.

Multi-valued logic (MVL) technology that utilizes more than two logic states has recently been reconsidered because of the demand for greater power saving in current binary logic systems. Extensive efforts have been invested in developing MVL devices with multiple threshold voltages by adopting negative differential transconductance and resistance. In this study, a reconfigurable, multiple negative-differential-resistance (m-NDR) device with an electric-field-induced tunability of multiple threshold voltages is reported, which comprises a BP/ReS2 heterojunction and a ReS2 /h-BN/metal capacitor. Tunability for the m-NDR phenomenon is achieved via the resistance modulation of the ReS2 layer by electrical pulses applied to the capacitor region. Reconfigurability is verified in terms of the function of an MVL circuit composed of a reconfigurable m-NDR device and a load transistor, wherein staggered-type and broken-type double peak-NDR device operations are adopted for ternary inverter and latch circuits, respectively.