Tunnel Field Effect Transistor with Ferroelectric Gate Insulator.

Ferroelectric tunnel field effect transistor (Fe-TFET) having improved DC performance in comparison to the conventional TFET (c-TFET) is proposed and investigated through the technology computer-aided design (TCAD) simulation. By inserting ferroelectric material into the gate insulator of TFET, enhanced on-current (Ion) is obtained. It is attributed to the polarization characteristic of the ferroelectric materials which brings the capacitance boosting effect. Through the TCAD simulation, the characteristics of the ferroelectric material for the optimal performance conditions are also studied.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

A novel fabrication method for the nanoscale tunneling field effect transistor.

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.

Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS).