In Situ Atomic-Scale Observation of Monolayer MoS2 Devices under High-Voltage Biasing via Transmission Electron Microscopy.

2D materials have great potential for not only device scaling but also various applications. To prompt the development of 2D electronics and optoelectronics, a better understanding of the limitation of materials is essential. Material failure caused by bias can lead to variations in device behavior and even electrical breakdown. In this study, the structural evolution of monolayer MoS2 with high bias is revealed via in situ transmission electron microscopy at the atomic scale. The biasing process is recorded and studied with the aid of aberration-corrected scanning transmission electron microscopy. The effects of electron beam irradiation and biasing are also discussed through the combination of experiments and theory. It is found that the Mo nanoclusters result from disintegration of MoS2 and sulfur depletion, which are induced by Joule heating. The thermal stress can also damage the MoS2 layer and form long cracks in both in situ and ex situ biasing cases. Investigation of the results obtained with different applied voltages helps to further verify the mechanism of evolution and provide a comprehensive study of the function of biasing.

Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design.

Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec-1) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 1013 cm-2 eV-1). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at Vdd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.