Recognizing Spatiotemporal Features by a Neuromorphic Network with Highly Reliable Ferroelectric Capacitors on Epitaxial GeSn Film.

Epitaxial GeSn (epi-GeSn) shows the capability to form ferroelectric capacitors (FeCAPs) with a higher remanent polarization (Pr) than epi-Ge. With the interface engineering by a high-k AlON, the reliability of the epi-GeSn-based FeCAPs is enhanced. Using the highly reliable FeCAP in series with a resistor as the synapse and axon, a simplified neuromorphic network based on a differentiator circuit is proposed. The network not only holds the leaky integrate-and-fire (LIF) function but is also capable of recognizing the spatiotemporal features, which sets it apart from other LIF neurons arising from the FeCAP-modulated leaky behavior of the potential on the axon by spiking-time-dependent plasticity. Furthermore, it is more energy efficient to operate, nondestructive to read, and simpler to fabricate by employing FeCAPs, making it eligible for emergent spiking neural network hardware accelerators.

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing.

Ferroelectric HfZrOx (Fe-HZO) with a larger remnant polarization (Pr) is achieved by using a poly-GeSn film as a channel material as compared with a poly-Ge film because of the lower thermal expansion that induces higher stress. Then two-stage interface engineering of junctionless poly-GeSn (Sn of ∼5.1%) ferroelectric thin-film transistors (Fe-TFTs) based on HZO was employed to improve the reliability characteristics. With stage I of NH3 plasma treatment on poly-GeSn and subsequent stage II of Ta2O5 interfacial layer growth, the interfacial quality between Fe-HZO and the poly-GeSn channel is greatly improved, which in turn enhances the reliability performance in terms of negligible Pr degradation up to 106 cycles (±2.7 MV/1 ms) and 96% Pr after a 10 year retention at 85 °C. Furthermore, to emulate the synapse plasticity of the human brain for neuromorphic computing, besides manifesting the capability of short-term plasticity, the devices also exhibit long-term plasticity with the characteristics of analog conductance (G) states of 80 levels (>6 bit), small linearity for potentiation and depression of -0.83 and 0.62, high symmetry, and moderate Gmax/Gmin of 9.6. By employing deep neural network, the neuromorphic system with poly-GeSn Fe-TFT synaptic devices achieves 91.4% pattern recognition accuracy. In addition, the learning algorithm of spike-timing-dependent plasticity based on spiking neural network is demonstrated as well. The results are promising for on-chip training, making it possible to implement neuromorphic computing by monolithic 3D ICs based on poly-GeSn Fe-TFTs.

Flash Memory Featuring Low-Voltage Operation by Crystalline ZrTiO4 Charge-Trapping Layer.

Crystalline ZrTiO4 (ZTO) in orthorhombic phase with different plasma treatments was explored as the charge-trapping layer for low-voltage operation flash memory. For ZTO without any plasma treatment, even with a high k value of 45.2, it almost cannot store charges due the oxygen vacancies-induced shallow-level traps that make charges easy to tunnel back to Si substrate. With CF4 plasma treatment, charge storage is still not improved even though incorporated F atoms could introduce additional traps since the F atoms disappear during the subsequent thermal annealing. On the contrary, nevertheless the k value degrades to 40.8, N2O plasma-treated ZTO shows promising performance in terms of 5-V hysteresis memory window by ±7-V sweeping voltage, 2.8-V flatband voltage shift by programming at +7 V for 100 µs, negligible memory window degradation with 105 program/erase cycles and 81.8% charge retention after 104 sec at 125 °C. These desirable characteristics are ascribed not only to passivation of oxygen vacancies-related shallow-level traps but to introduction of a large amount of deep-level bulk charge traps which have been proven by confirming thermally excited process as the charge loss mechanism and identifying traps located at energy level beneath ZTO conduction band by 0.84 eV~1.03 eV.

N-MOSFETs Formed on Solid Phase Epitaxially Grown GeSn Film with Passivation by Oxygen Plasma Featuring High Mobility.

Solid phase epitaxially grown GeSn was employed as the platform to assess the eligibility of direct O2 plasma treatment on GeSn surface for passivation of GeSn N-MOSFETs. It has been confirmed that O2 plasma treatment forms a GeSnO(x) film on the surface and the GeSnO(x) topped by in situ Al2O3 constitutes the gate stack of GeSn MOS devices. The capability of the surface passivation was evidenced by the low interface trap density (D(it)) of 1.62 × 10(11) cm(-2) eV(-1), which is primarily due to the formation of Ge-O and Sn-O bonds at the surface by high density/reactivity oxygen radicals that effectively suppress dangling bonds and decrease gap states. The good D(it) not only makes tiny frequency dispersion in the characterization of GeSn MOS capacitors, but results in GeSn N-MOSFETs with outstanding peak electron mobility as high as 518 cm(2)/(V s) which outperforms other devices reported in the literature due to reduced undesirable carrier scattering. In addition, the GeSn N-MOSFETs also exhibit promising characteristics in terms of acceptable subthreshold swing of 156 mV/dec and relatively large I(ON)/I(OFF) ratio more than 4 orders. Moreover, the robust reliability in terms small V(t) variation against high field stress attests the feasibility of using the O2 plasma-treated passivation to advanced GeSn technology.

Low-voltage operation of ZrO2-gated n-type thin-film transistors based on a channel formed by hybrid phases of SnO and SnO2.

With SnO typically regarded as a p-type oxide semiconductor, an oxide semiconductor formed by hybrid phases of mainly SnO and a small amount of SnO2 with an average [O]/[Sn] ratio of 1.1 was investigated as a channel material for n-type thin-film transistors (TFTs). Furthermore, an appropriate number of oxygen vacancies were introduced into the oxide during annealing at 400 °C in ambient N2, making both SnO and SnO2 favorable for current conduction. By using high-κ ZrO2 with a capacitance equivalent thickness of 13.5 nm as the gate dielectric, the TFTs processed at 400 °C demonstrated a steep subthreshold swing (SS) of 0.21 V/dec, and this can be ascribed to the large gate capacitance along with a low interface trap density (Dit) value of 5.16 × 10(11) cm(-2) eV(-1). In addition, the TFTs exhibit a relatively high electron mobility of 7.84 cm(2)/V·s, high ON/OFF current ratios of up to 2.5 × 10(5), and a low gate leakage current at a low operation voltage of 3 V. The TFTs also prove its high reliability performance by showing negligible degradation of SS and threshold voltage (VT) against high field stress (-10 MV/cm). When 3% oxygen annealing is combined with a thinner channel thickness, TFTs with even higher ION/IOFF ratios exceeding 10(7) can also be obtained. With these promising characteristics, the overall performance of the TFTs displays competitive advantages compared with other n-type TFTs formed on binary or even some multicomponent oxide semiconductors and paves a promising and economic avenue to implement an n-type oxide semiconductor without doping for production-worthy TFT technology. Most importantly, when combined with the typical SnO-based p-type oxide semiconductor, it would usher in a new era in achieving high-performance complementary metal oxide semiconductor circuits by using the same SnO-based oxide semiconductor.

ZnO/NiO diode-based charge-trapping layer for flash memory featuring low-voltage operation.

A stacked oxide semiconductor of n-type ZnO/p-type NiO with diode behavior was proposed as the novel charge-trapping layer to enable low-voltage flash memory for green electronics. The memory performance outperforms that of other devices with high κ and a nanocrystal-based charge-trapping layer in terms of a large hysteresis memory window of 2.02 V with ±3 V program/erase voltage, a high operation speed of 1.88 V threshold voltage shift by erasing at -4 V for 1 ms, negligible memory window degradation up to 10(5) operation cycles, and 16.2% charge loss after 10 years of operation at 85 °C. The promising electrical characteristics can be explained by the negative conduction band offset with respect to Si of ZnO that is beneficial to electron injection and storage, the large number of trapping sites of NiO that act as other good storage media, and most importantly the built-in electric field between n-type ZnO and p-type NiO that provides a favorable electric field for program and erase operation. The process of diode-based flash memory is fully compatible with incumbent VLSI technology, and utilization of the built-in electric field ushers in a new avenue of accomplishing green flash memory.

Simplified ZrTiO x -based RRAM cell structure with rectifying characteristics by integrating Ni/n + -Si diode.

A simplified one-diode one-resistor (1D1R) resistive switching memory cell that uses only four layers of TaN/ZrTiO x /Ni/n(+)-Si was proposed to suppress sneak current where TaN/ZrTiO x /Ni can be regarded as a resistive-switching random access memory (RRAM) device while Ni/n(+)-Si acts as an Schottky diode. This is the first RRAM cell structure that employs metal/semiconductor Schottky diode for current rectifying. The 1D1R cell exhibits bipolar switching behavior with SET/RESET voltage close to 1 V without requiring a forming process. More importantly, the cell shows tight resistance distribution for different states, significantly rectifying characteristics with forward/reverse current ratio higher than 10(3) and a resistance ratio larger than 10(3) between two states. Furthermore, the cell also displays desirable reliability performance in terms of long data retention time of up to 10(4) s and robust endurance of 10(5) cycles. Based on the promising characteristics, the four-layer 1D1R structure holds the great potential for next-generation nonvolatile memory technology.