Vapor-phase synthesis of a reagent-free self-healing polymer film with rapid recovery of toughness at room temperature and under ambient conditions.

A rapidly self-healable polymer is highly desirable but challenging to achieve. Herein, we developed an elastomeric film with instant self-healing ability within 10 s at room temperature. For this purpose, a series of copolymers of poly(glycidyl methacrylate-co-2-hydroxyethyl acrylate) (poly(GMA-co-HEA), or pGH) were synthesized in the vapor phase via an initiated chemical vapor deposition (iCVD) process. The elastomer includes a large amount of hydroxyl groups in the 2-hydroxyethyl acrylate (HEA) moiety capable of forming rapid, reversible hydrogen bonding at room temperature, while glycidyl methacrylate (GMA) with a rigid methacrylic backbone chain in the copolymer provides mechanical robustness to the elastic copolymer. With the optimized copolymer composition, pGH indeed showed instant recovery of the toughness within a minute; a completely divided specimen could be welded within a minute at room temperature and under ambient conditions simply by placing the pieces in close contact, which showed the outstanding recovery performance of elastic modulus (93.2%) and toughness (15.6 MJ m-3). The rapid toughness recovery without supplementing any external energy or reagents (e.g. light, temperature, or catalyst) at room temperature and under ambient conditions will be useful in future wearable electronics and soft robotics applications.

Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

Influence of Self-Heating Effect on Interface Trap Generation in Highly Flexible Single-Crystalline Si Nanomembrane Transistors.

We analyze the interface trap states generated by the self-heating effect in flexible single-crystalline Si nanomembrane (sc-Si NM) transistors. Despite the excellent device performance (Subthreshold swing: ~61 mV/dec, Ion/off: ~109, Nit: ~5 × 1010 cm-2, µeff: ~250 cm²/V·s) and mechanical flexibility (RB,min ═ 1 mm) of sc-Si NM transistors on a polymer substrate, they are vulnerable to thermal reliability issues due to the poor thermal conductivity (κ < 1 W/m·K) of the polymer substrate. Understanding the detailed mechanism driving heat-related device degradation is key to improving device reliability, life expectancy, and overall device performance. Thus, a charge pumping method was employed to systematically analyze the device degradation caused by the self-heating effect. This enabled the interface trap density to be investigated for the flexible sc-Si NM transistors on a polymer substrate after a bias stress. For comparison, a heat spreading layer (HSL) made using a 1-µm thick Ag film (κ~400 W/m·K) was integrated into the sc-Si NM device to mitigate the self-heating effect. The results showed that the interface trap density was proportional to the self-heating effect. This facilitated the fundamental understanding of the self-heating effect of flexible sc-Si NM transistors, opening a robust route to realizing high performance flexible devices using sc-Si NM.

A High-Performance Top-Gated Graphene Field-Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric.

A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (VDirac ) of the graphene FET can thus be systematically controlled. In particular, the VDirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm2 V-1 s-1 , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications.

Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications.

A 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications.

Compliment Graphene Oxide Coating on Silk Fiber Surface via Electrostatic Force for Capacitive Humidity Sensor Applications.

Cylindrical silk fiber (SF) was coated with Graphene oxide (GO) for capacitive humidity sensor applications. Negatively charged GO in the solution was attracted to the positively charged SF surface via electrostatic force without any help from adhesive intermediates. The magnitude of the positively charged SF surface was controlled through the static electricity charges created on the SF surface. The GO coating ability on the SF improved as the SF's positive charge increased. The GO-coated SFs at various conditions were characterized using an optical microscope, scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS), Raman spectroscopy, and LCR meter. Unlike the intact SF, the GO-coated SF showed clear response-recovery behavior and well-behaved repeatability when it was exposed to 20% relative humidity (RH) and 90% RH alternatively in a capacitive mode. This approach allows humidity sensors to take advantage of GO's excellent sensing properties and SF's flexibility, expediting the production of flexible, low power consumption devices at relatively low costs.

Free-Standing Graphene Thermophone on a Polymer-Mesh Substrate.

A graphene thermoacoustic loudspeaker with a thin polymer mesh is fabricated using screen-printing. An experiment with substrates of various free-standing areas shows that a higher sound pressure level can be achieved as compared to previously reported graphene thermoacoustic loudspeakers. Moreover, a modified equation to predict the sound pressure level of the thermoacoustic loudspeaker with a thin and patterned substrate is proposed and verified by experimental results.

Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics.

Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.

Metal-etching-free direct delamination and transfer of single-layer graphene with a high degree of freedom.

A method of graphene transfer without metal etching is developed to minimize the contamination of graphene in the transfer process and to endow the transfer process with a greater degree of freedom. The method involves direct delamination of single-layer graphene from a growth substrate, resulting in transferred graphene with nearly zero Dirac voltage due to the absence of residues that would originate from metal etching. Several demonstrations are also presented to show the high degree of freedom and the resulting versatility of this transfer method.

Improvement of Gate Dielectric Integrity Using O2 Plasma Treatment Prior to Atomic Layer Deposition on Chemical Vapor Deposition Grown Graphene.

We report that oxygen plasma treatment of CVD-grown graphene can improve the integrity of an aluminum oxide layer deposited by atomic layer deposition. There is an optimum process window for treatment with O2 plasma which does not cause serious degradation in the quality of the graphene, but provides significant improvement in the gate dielectric integrity in relation to capacitance uniformity, leakage current, and dielectric breakdown voltage.

High-angle tilt boundary graphene domain recrystallized from mobile hot-wire-assisted chemical vapor deposition system.

Crystallization of materials has attracted research interest for a long time, and its mechanisms in three-dimensional materials have been well studied. However, crystallization of two-dimensional (2D) materials is yet to be challenged. Clarifying the dynamics underlying growth of 2D materials will provide the insight for the potential route to synthesize large and highly crystallized 2D domains with low defects. Here, we present the growth dynamics and recrystallization of 2D material graphene under a mobile hot-wire assisted chemical vapor deposition (MHW-CVD) system. Under local but sequential heating by MHW-CVD system, the initial nucleation of nanocrystalline graphenes, which was not extended into the growth stage due to the insufficient thermal energy, took a recrystallization and converted into a grand single crystal domain. During this process, the stitching-like healing of graphene was also observed. The local but sequential endowing thermal energy to nanocrystalline graphenes enabled us to simultaneously reveal the recrystallization and healing dynamics in graphene growth, which suggests an alternative route to synthesize a highly crystalline and large domain size graphene. Also, this recrystallization and healing of 2D nanocrystalline graphenes offers an interesting insight on the growth mechanism of 2D materials.

Synthesis of monolayer graphene having a negligible amount of wrinkles by stress relaxation.

For the chemical vapor deposition (CVD) of graphene, the grain growth of the catalyst metal and thereby surface roughening are unavoidable during the high temperature annealing for the graphene synthesis. Considering that nanoscale wrinkles and poor uniformity of synthesized graphene originate from the roughened metal surface, improving surface flatness of metal thin films is one of the key factors to synthesize high quality graphene. Here, we introduce a new method for graphene synthesis for fewer wrinkle formation on a catalyst metal. The method utilizes a reduced graphene oxide (rGO) interfacial layer between the metal film and the wafer substrate. The rGO interlayer releases the residual stress of the metal thin film and thereby suppresses stress-induced metal grain growth. This technique makes it possible to use much thinner nickel films, leading to a dramatic suppression of RMS roughness (~3 nm) of the metal surface even after high temperature annealing. It also endows excellent control of the graphene thickness due to the reduced amount of total carbon in the thin nickel film. The synthesized graphene layer having negligible amount of wrinkles exhibits excellent thickness uniformity (91% coverage of monolayer) and very high carrier mobility of ~15,000 cm(2)/V·s.

Determination of work function of graphene under a metal electrode and its role in contact resistance.

Although the work function of graphene under a given metal electrode is critical information for the realization of high-performance graphene-based electronic devices, relatively little relevant research has been carried out to date. In this work, the work function values of graphene under various metals are accurately measured for the first time through a detailed analysis of the capacitance-voltage (C-V) characteristics of a metal-graphene-oxide-semiconductor (MGOS) capacitor structure. In contrast to the high work function of exposed graphene of 4.89-5.16 eV, the work function of graphene under a metal electrode varies depending on the metal species. With a Cr/Au or Ni contact, the work function of graphene is pinned to that of the contacted metal, whereas with a Pd or Au contact the work function assumes a value of ∼4.62 eV regardless of the work function of the contact metal. A study of the gate voltage dependence on the contact resistance shows that the latter case provides lower contact resistance.

Direct measurement of adhesion energy of monolayer graphene as-grown on copper and its application to renewable transfer process.

Direct measurement of the adhesion energy of monolayer graphene as-grown on metal substrates is important to better understand its bonding mechanism and control the mechanical release of the graphene from the substrates, but it has not been reported yet. We report the adhesion energy of large-area monolayer graphene synthesized on copper measured by double cantilever beam fracture mechanics testing. The adhesion energy of 0.72 ± 0.07 J m(-2) was found. Knowing the directly measured value, we further demonstrate the etching-free renewable transfer process of monolayer graphene that utilizes the repetition of the mechanical delamination followed by the regrowth of monolayer graphene on a copper substrate.

A non-invasive approach to the resistive switching physical model of ultra-thin organic-inorganic dielectric-based ReRAMs.

The race to next-generation non-volatile memory is on, and ultra-thin (<5 nm) organic-inorganic hybrid dielectric-based ReRAMs are a top contender. However, their extremely small thickness hinders their processability through material characterization techniques, leaving gaps in our understanding of the resistive switching (RS) dynamics in the hybrid dielectric layer. Furthermore, the poor uniformity of key switching parameters remains a persistent issue in ReRAMs, which impedes any trends to be clearly defined through electrical characterization. This work uses electrical manipulation through a ramped-pulse series (RPS) method to improve the voltage and resistance fluctuations in the reset process of ultra-thin Al/Hf-hybrid/Ni devices. By analyzing their electrical behavior under different pulse and temperature conditions, we propose a comprehensive physical model that describes the operating mechanism of the device. Our results confirm the coexistence in the conductive filament (CF) of a hybrid metallic portion composed of Al and Hf3Al2 and an oxygen vacancy portion. The vacancies are found to play a significant role in RS, with most of them generated during the CF forming process and participating to different degrees in the filament rupture of the RPS-processed and non-RPS-processed devices via Joule heating, drift, and Fick forces. Additionally, we identify the cause of switching failure events to be based on the presence of an Al2O3 interlayer in the Al/Hf-hybrid interface.

The Effect of Alkyl Chain Length in Organic Semiconductor and Surface Polarity of Polymer Dielectrics in Organic Thin-Film Transistors (OTFTs).

The interface between dielectric and organic semiconductor is critically important in determining organic thin-film transistor (OTFT) performance. Surface polarity of the dielectric layer can hinder charge transport characteristics, which has restricted utilization of polymeric dielectric materials containing polar functional groups. Herein, the electrical characteristics of OTFTs are analyzed depending on the alkyl chain length of organic semiconductors and surface polarity of polymer dielectrics. High-performance dibenzothiopheno[6,5-b:6',5'-f]thieno[3,2-b]thiophene (DBTTT) and newly synthesized its alkylated derivatives (C6-DBTTT and C10-DBTTT) are utilized as organic semiconductors. As dielectric layers, non-polar poly(1,3,5-trimethyl-1,3,5-trivinylcyclitrisiloxane) (pV3D3) and poly(2-cyanoethyl acrylate-co-diethylene glycol divinyl ether) [p(CEA-co-DEGDVE)] with polar cyanide functionality are utilized. The fabricated OTFTs with pV3D3 commonly exhibit the excellent charge transport characteristics. In addition, the OTFT performance is improved with lengthening the alkyl chain in organic semiconductors, which can be attributed to the molecular orientation of semiconductors. On the other hand, non-alkylated DBTTT OTFTs with polar p(CEA-co-DEGDVE) show relatively poor electrical characteristics, while their performance is drastically enhanced with the alkylated DBTTTs. The ultraviolet photoelectron spectroscopy (UPS) reveals that surface polarity of the dielectric layer can be abated with alkyl chain in organic semiconductors. It is believed that this study can provide a useful insight to optimize dielectric/semiconductor interface to achieve high-performance OTFTs.

Electromagnetic interference shielding effectiveness of monolayer graphene.

We report the first experimental results on the electromagnetic interference (EMI) shielding effectiveness (SE) of monolayer graphene. The monolayer CVD graphene has an average SE value of 2.27 dB, corresponding to ~40% shielding of incident waves. CVD graphene shows more than seven times (in terms of dB) greater SE than gold film. The dominant mechanism is absorption rather than reflection, and the portion of absorption decreases with an increase in the number of graphene layers. Our modeling work shows that plane-wave theory for metal shielding is also applicable to graphene. The model predicts that ideal monolayer graphene can shield as much as 97.8% of EMI. This suggests the feasibility of manufacturing an ultrathin, transparent, and flexible EMI shield by single or few-layer graphene.

Graphene gate electrode for MOS structure-based electronic devices.

We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.

Graphene oxide thin films for flexible nonvolatile memory applications.

There has been strong demand for novel nonvolatile memory technology for low-cost, large-area, and low-power flexible electronics applications. Resistive memories based on metal oxide thin films have been extensively studied for application as next-generation nonvolatile memory devices. However, although the metal oxide based resistive memories have several advantages, such as good scalability, low-power consumption, and fast switching speed, their application to large-area flexible substrates has been limited due to their material characteristics and necessity of a high-temperature fabrication process. As a promising nonvolatile memory technology for large-area flexible applications, we present a graphene oxide based memory that can be easily fabricated using a room temperature spin-casting method on flexible substrates and has reliable memory performance in terms of retention and endurance. The microscopic origin of the bipolar resistive switching behavior was elucidated and is attributed to rupture and formation of conducting filaments at the top amorphous interface layer formed between the graphene oxide film and the top Al metal electrode, via high-resolution transmission electron microscopy and in situ X-ray photoemission spectroscopy. This work provides an important step for developing understanding of the fundamental physics of bipolar resistive switching in graphene oxide films, for the application to future flexible electronics.

Impact of Al doping on a hydrothermally synthesized ß-Ga2O3 nanostructure for photocatalysis applications.

Aluminum (Al)-doped beta-phase gallium oxide (ß-Ga2O3) nanostructures with different Al concentrations (0 to 3.2 at%) are synthesized using a hydrothermal method. The single phase of the ß-Ga2O3 is maintained without intermediate phases up to Al 3.2 at% doping. As the Al concentration in the ß-Ga2O3 nanostructures increases, the optical bandgap of the ß-Ga2O3 increases from 4.69 (Al 0%) to 4.8 (Al 3.2%). The physical, chemical, and optical properties of the Al-doped ß-Ga2O3 nanostructures are correlated with photocatalytic activity via the degradation of a methylene blue solution under ultraviolet light (254 nm) irradiation. The photocatalytic activity is enhanced by doping a small amount of substitutional Al atoms (0.6 at%) that presumably create shallow level traps in the band gap. These shallow traps retard the recombination process by separating photogenerated electron-hole pairs. On the other hand, once the Al concentration in the Ga2O3 exceeds 0.6 at%, the crystallographic disorder, oxygen vacancy, and grain boundary-related defects increase as the Al concentration increases. These defect-related energy levels are broadly distributed within the bandgap, which act as carrier recombination centers and thereby degrade the photocatalytic activity. The results of this work provide new opportunities for the synthesis of highly effective ß-Ga2O3-based photocatalysts that can generate hydrogen gas and remove harmful volatile organic compounds.