Three-dimensional wavelength-division multiplexing interconnects based on a low-loss SixNy arrayed waveguide grating.

We fabricate three-dimensional wavelength-division multiplexing (3D-WDM) interconnects comprising three SixNy layers using a CMOS-compatible process. In these interconnects, the optical signals are coupled directly to a SixNy grating coupler in the middle SixNy layer and demultiplexed by a 1 × 4 SixNy array waveguide grating (AWG). The demultiplexed optical signals are interconnected from the middle SixNy layer to the bottom and top SixNy layers by four SiOxNy interlayer couplers. A low insertion loss and low crosstalk are achieved in the AWG. The coupling losses of the SiOxNy interlayer couplers and SixNy grating coupler are ∼1.52 dB and ∼4.2 dB, respectively.

NDR-effect vertical-illumination-type Ge-on-Si avalanche photodetector.

We present the enhanced performances of a vertical-illumination-type Ge-on-Si avalanche photodetector based on internal RF-gain effects operating up to 50 Gb/s. A fabricated Ge-on-Si avalanche photodetector (APD) exhibits three operational voltage regions associated with different aspects of the current (DC) gain and bandwidth characteristics. The measured current-voltage (I-V) curve of a Ge-on-Si APD exhibits a negative photoconductance (negative differential resistance [NDR]) in a high bias region beyond the avalanche breakdown voltage (V br ), where a device shows good eye openings up to 50 Gb/s (non-return-to-zero [NRZ] signal) with further improved signal-to-noise ratios and signal amplitudes. A ROSA packaged module, wherein a fabricated Ge-on-Si APD is wire-bonded to a commercial TIA with a ∼75% optical alignment for λ∼1310 nm and biased at a lower voltage than the V br , exhibits the sensitivities of -18.9 and -15.3 dBm for 30 and 35 Gb/s, respectively, and -13.9 dBm for 40 Gb/s at a 10-12 bit error rate. The experimental results indicate that considerable improvement in a module performance can be expected by utilizing the Ge-on-Si APD operated in the NDR region with a properly customized TIA.

Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~1550 nm.

We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10(-12). The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of -11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of -2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10(-15) BER at 25 Gb/s, 10(-14) BER at 28 Gb/s, and 6 x 10(-13) BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.

Performance improvement in silicon arrayed waveguide grating by suppression of scattering near the boundary of a star coupler.

We investigate the reduction of transition loss across the star coupler boundary in a silicon arrayed waveguide grating (AWG) by suppressing multimode generation and scattering near the boundary of a star coupler. Eight-channel silicon AWGs were designed with optimal conditions based on enhanced field matching in combination with ultrashallow etched structures. The fabricated AWG demonstrates an insertion loss down to 0.63 dB with a cross talk of -23 to -25.3 dB, exhibiting ~0.8 dB improvement of insertion loss and ~4 dB improvement of cross talk compared to the Si AWG fabricated with a conventional double-etch technique.

Compact-sized high-modulation-efficiency silicon Mach-Zehnder modulator based on a vertically dipped depletion junction phase shifter for chip-level integration.

We present small-sized depletion-type silicon Mach-Zehnder (MZ) modulator with a vertically dipped PN depletion junction (VDJ) phase shifter based on a CMOS compatible process. The fabricated device with a 100 µm long VDJ phase shifter shows a VπLπ of ∼0.6 V·cm with a 3 dB bandwidth of ∼50 GHz at -2 V bias. The measured extinction ratios are 6 and 5.3 dB for 40 and 50 Gb/s operation under 2.5 Vpp differential drive, respectively. On-chip insertion loss is 3 dB for the maximum optical transmission. This includes the phase-shifter loss of 1.88 dB/100 µm, resulting mostly from the extra optical propagation loss through the polysilicon-plug structure for electrical contact, which can be readily minimized by utilizing finer-scaled lithography nodes. The experimental result indicates that a compact depletion-type MZ modulator based on the VDJ scheme can be a potential candidate for future chip-level integration.

A fiber-to-chip coupler based on Si/SiON cascaded tapers for Si photonic chips.

This paper reports a fiber-to-chip coupler consisting of a silicon inverted taper and a silicon oxynitride (SiON) double stage taper, where the cascaded taper structure enables adiabatic mode transfer between a submicron silicon waveguide and a single mode fiber. The coupler, fabricated by a simplified process, demonstrates an average coupling loss of 3.6 and 4.2 dB for TM and TE polarizations, respectively, with a misalignment tolerance of ± 2.2 µm for 1 dB loss penalty.

High-performance photoreceivers based on vertical-illumination type Ge-on-Si photodetectors operating up to 43 Gb/s at λ~1550nm.

We present high-sensitivity photoreceivers based on a vertical- illumination-type 100% Ge-on-Si p-i-n photodetectors (PDs), which operate up to 50 Gb/s with high responsivity. A butterfly-packaged photoreceiver using a Ge PD with 3-dB bandwidth (f(-3dB)) of 29 GHz demonstrates the sensitivities of -10.15 dBm for 40 Gb/s data rate and -9.47 dBm for 43 Gb/s data rate, at BER of 10(-12) and λ ~1550 nm. Also a photoreceiver based on a Ge PD with f(-3dB)~19 GHz shows -14.14 dBm sensitivity at 25 Gb/s operation. These results prove the high performance levels of vertical-illumination type Ge PDs ready for practical high-speed network applications.

Echelle grating silicon multi/demultiplexers with single-reflection total internal reflectors.

We present a silicon-on-insulator Echelle grating 8-channel demutiplexer showing characteristic features, average insertion loss 2.4 dB measured at 1520~1570 nm, adjacent channel crosstalk 15-18 dB, and channel spacing 11.9 nm. Our Echelle grating is remarked by a total internal reflector (TIR) which reflects incident light by a single reflection in contrast to the double reflections of retro-reflector TIR Echelle gratings.

Si micro-ring MUX/DeMUX WDM filters.

We demonstrate 3rd order micro-ring filters, 100 GHz-spaced 16 channels and 50 GHz-spaced 32 channels. Fabrication-induced resonant wavelength errors, σ = 0.237 nm, and temperature-dependent wavelength shift, 0.043 nm/°C tolerable to ΔT>10 °C, has been measured on filters based on the fundamental TM mode. The problem of CMOS-compatible photolithography is solved, while maintaining a small radius, R = 9 µm. As some dummy channels are arranged, it is shown that an on-chip optical network for many cores CPU can be constructed by 16 channel ring filters with the currently available technology.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13µm CMOS interface IC chips were hybrid-integrated.

High-sensitivity 10 Gbps Ge-on-Si photoreceiver operating at lambda approximately 1.55 microm.

We present a high-sensitivity photoreceiver based on a vertical- illumination-type 100% Ge-on-Si photodetector. The fabricated p-i-n photodetector with a 90 microm-diameter mesa shows the -3 dB bandwidth of 7.7 GHz, and the responsivity of 0.9 A/W at lambda approximately 1.55 microm, corresponding to the external quantum efficiency of 72%. A TO-can packaged Ge photoreceiver exhibits the sensitivity of -18.5 dBm for a BER of 10(-12) at data rate of 10 Gbps. This result proves the capability of a cost-effective 100% Ge-on-Si photoreceiver which can readily replace the III-V counterparts for optical communications.

High-modulation efficiency silicon Mach-Zehnder optical modulator based on carrier depletion in a PN Diode.

We present a high phase-shift efficiency Mach-Zehnder silicon optical modulator based on the carrier-depletion effect in a highly-doped PN diode with a small waveguide cross-sectional area. The fabricated modulator show a V(pi)L(pi) of 1.8 V x cm and phase shifter loss of 4.4 dB/mm. A device using a 750 microm-long phase-shifter exhibits an eye opening at 12.5 Gbps with an extinction ratio of 3 dB. Also, an extinction ratio of 7 dB is achieved at 4 Gbps for a device with a 2 mm-long phase shifter. Further enhancement of the extinction ratio at higher operating speed can be achieved using a travelling-wave electrode design and the optimal doping.

Adjusting resonant wavelengths and spectral shapes of ring resonators using a cladding SiN layer or KOH solution.

It is shown that the resonant frequencies and the transmission spectra of ring resonators can be adjusted by depositing or etching the cladding nitride layer on the ring waveguide without introducing an extra loss or extra variations of channel spacing. The cladding nitride layer increases the minimum width of the gap in the coupling region to larger than 150nm which makes it possible to consider photolithography instead of E-beam lithography for the typical design rule of ring filters. KOH silicon etching can also adjust not only the resonance frequencies but also coupling coefficients with a small sacrifice of guiding loss.

Enhancing alignment tolerance of silicon waveguide by using a wide grating coupler.

We fabricate a 20 um wide grating coupler for a single-mode thermally-expanded-core (TEC) fiber, in order to enhance positional tolerance in alignment. The minimal coupling loss is measured at 5 dB per facet and the optical 3 dB bandwidth is measured at 40 nm. The 3 dB alignment tolerance is measured at +-7.5 microm in horizontal direction and +290 microm in vertical direction. The 1 dB alignment tolerance is measured at +-4.2 microm in horizontal direction and +125 microm in vertical direction. The alignment tolerance is enhanced twice in horizontal direction and four times in vertical direction, compared with the coupling of a standard single-mode fiber to a standard 10 microm wide grating coupler which is also fabricated in this experiment.

12.5 Gbps optical modulation of silicon racetrack resonator based on carrier-depletion in asymmetric p-n diode.

We present a high speed optical modulation using carrier depletion effect in an asymmetric silicon p-n diode resonator. To optimize coupling efficiency and reduce bending loss, two-step-etched waveguide is used in the racetrack resonator with a directional coupler. The quality factor of the resonator with a circumference of 260 um is 9,482, and the DC on/off ratio is 8 dB at -12V. The device shows the 3dB bandwidth of approximately8 GHz and the data transmission up to 12.5Gbit/s.

Controlling temperature dependence of silicon waveguide using slot structure.

We show that the temperature dependence of a silicon waveguide can be controlled well by using a slot waveguide structure filled with a polymer material. Without a slot, the amount of temperature-dependent wavelength shift for TE mode of a silicon waveguide ring resonator is very slightly reduced from 77 pm/ degrees C to 66 pm/ degrees C by using a polymer (WIR30-490) upper cladding instead of air upper cladding. With a slot filled with the same polymer, however, the reduction of the temperature dependence is improved by a pronounced amount and can be controlled down to -2 pm/ degrees C by adjusting several variables of the slot structure, such as the width of the slot between the pair of silicon wires, the width of the silicon wire pair, and the height of the silicon slab in our experiment. This measurement proves that a reduction in temperature dependence can be improved about 8 times more by using the slot structure.

Photo-assisted electrical gating in a two-terminal device based on vanadium dioxide thin film.

For electrical devices based on vanadium dioxide thin film, various methods have been implemented on the electrical gating of the devices. In this paper, a photo-assisted electrical gating in a two-terminal device is demonstrated based on vanadium dioxide thin film, instead of a three-terminal device with a gate terminal, by illuminating infrared light directly onto the film. Based on the light-induced phase transition, the threshold voltage of the device, in which an abrupt current jump take places, was theoretically anticipated to be controlled (electrically gated) by adjusting the light intensity. Finally, the prediction was experimentally verified.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.