On-Chip Annealing Using Embedded Micro-Heater for Highly Sensitive and Selective Gas Detection.

The demand for gas sensing systems that enable fast and precise gas recognition is growing rapidly. However, substantial challenges arise from the complex fabrication process of sensor arrays, time-consuming data transmission to an external processor, and high energy consumption in multi-stage data processing. In this study, a gas sensing system using on-chip annealing for fast and power-efficient gas detection is proposed. By utilizing a micro-heater embedded in the gas sensor, the sensing material of adjacent sensors in the same substrate can be easily varied without further fabrication steps. The response to oxidizing gas is constrained in metal oxide (MOX) sensing material with small grain sizes, as the depletion width of grain cannot extend beyond the grain size during the gas reaction. On the other hand, the response to reducing gases and humidity, which decrease the depletion width, is less affected by grain sizes. A readout circuit integrating a differential amplifier and dual FET-type gas sensors effectively emphasizes the response to oxidizing gases by canceling the response to reducing gases and humidity. The selective on-chip annealing method is applicable to various MOX sensing materials, demonstrating its potential for application in commercial fields due to its simplicity and expandability.

Simulation of a randomly percolated CNT network for an improved analog physical unclonable function.

Carbon nanotube networks (CNTs)-based devices are well suited for the physically unclonable function (PUF) due to the inherent randomness of the CNT network, but CNT networks can vary significantly during manufacturing due to various controllable process conditions, which have a significant impact on PUF performance. Therefore, optimization of process conditions is essential to have a PUF with excellent performance. However, because it is time-consuming and costly to fabricate directly under various conditions, we implement randomly formed CNT network using simulation and confirm the variable correlation of the CNT network optimized for PUF performance. At the same time, by implementing an analog PUF through simulation, we present a 2D patterned PUF that has excellent security and can compensate for error occurrence problems. To evaluate the performance of analog PUF, a new evaluation method different from the existing digital PUF is proposed, and the PUF performance is compared according to two process variables, CNT density and metallic CNT ratio, and the correlation with PUF performance is confirmed. This study can serve as a basis for research to produce optimized CNT PUF by applying simulation according to the needs of the process of forming a CNT network.

Gate Capacitance Coupling of Double-Gate Carbon Nanotube Network Transistors.

Carbon nanotube (CNT) network channels constructed using a high-purity CNT solution for use in CNT thin-film transistors have the advantages of the possibility of requiring a low-temperature process and needing no special equipment. However, there are empty spaces between individual CNTs, resulting in unexpected effects. In this study, double-gate (DG) CNT network transistors were fabricated and measured in four different configurations to observe the capacitive coupling effects between the top gate (TG) and bottom gate (BG) in the DG structure. As a result, the electrical characteristics measured with the BG with a thicker gate oxide while floating the TG were similar to those measured with the TG with a thinner gate oxide. A comparison of the measured transfer curves showed that TG and BG were strongly coupled through the empty spaces in the channels. In addition, we evaluated the capacitance coupling effect due to changes in the CNT density, which is closely related to the empty space of the network channel. Finally, we proposed a method to determine the effective gate capacitance by considering the empty spaces between CNTs, which enabled the accurate evaluation of mobility. The effects of these materials were demonstrated by fabricating transistors using Al2O3, HfO2, and ZrO2 as TG oxide materials. By focusing on considerations based on the properties of CNT materials, our study provides valuable insights into accurate electrical modeling and potential advancements in CNT-based devices.

Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory.

Neuromorphic hardware using nonvolatile analog synaptic devices provides promising advantages of reducing energy and time consumption for performing large-scale vector-matrix multiplication (VMM) operations. However, the reported training methods for neuromorphic hardware have appreciably shown reduced accuracy due to the nonideal nature of analog devices, and use conductance tuning protocols that require substantial cost for training. Here, we propose a novel hybrid training method that efficiently trains the neuromorphic hardware using nonvolatile analog memory cells, and experimentally demonstrate the high performance of the method using the fabricated hardware. Our training method does not rely on the conductance tuning protocol to reflect weight updates to analog synaptic devices, which significantly reduces online training costs. When the proposed method is applied, the accuracy of the hardware-based neural network approaches to that of the software-based neural network after only one-epoch training, even if the fabricated synaptic array is trained for only the first synaptic layer. Also, the proposed hybrid training method can be efficiently applied to low-power neuromorphic hardware, including various types of synaptic devices whose weight update characteristics are extremely nonlinear. This successful demonstration of the proposed method in the fabricated hardware shows that neuromorphic hardware using nonvolatile analog memory cells becomes a more promising platform for future artificial intelligence.

Wafer-scale striped network transistors based on purified semiconducting carbon nanotubes for commercialization.

Highly purified and solution-processed semiconducting carbon nanotubes (s-CNTs) have developed rapidly over the past several decades and are near-commercially available materials that can replace silicon due to its large-area substrate deposition and room-temperature processing compatibility. However, the more s-CNTs are purified, the better their electrical performance, but considerable effort and long centrifugation time are required, which can limit commercialization due to high manufacturing costs. In this work, we therefore fabricated 'striped' CNT network transistor across industry-standard 8 inch wafers. The stripe-structured channel is effective in lowering the manufacturing cost because it can maintain good device performance without requiring high-purity s-CNTs. We evaluated the electrical performances and their uniformity by demonstrating striped CNT network transistors fabricating from various s-CNT solutions (e.g. 99%, 95%, and 90%) in 8 inch wafers. From our results, we concluded that by optimizing the CNT network configurations, CNTs can be sufficiently utilized for commercialization technology even at low semiconducting purity. Our approach can serve as a critical foundation for future low-cost commercial CNT electronics.

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons.

Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

Short-Term Memory Characteristics of IGZO-Based Three-Terminal Devices.

A three-terminal synaptic transistor enables more accurate controllability over the conductance compared with traditional two-terminal synaptic devices for the synaptic devices in hardware-oriented neuromorphic systems. In this work, we fabricated IGZO-based three-terminal devices comprising HfAlOx and CeOx layers to demonstrate the synaptic operations. The chemical compositions and thicknesses of the devices were verified by transmission electron microscopy and energy dispersive spectroscopy in cooperation. The excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), short-term potentiation (STP), and short-term depression (STD) of the synaptic devices were realized for the short-term memory behaviors. The IGZO-based three-terminal synaptic transistor could thus be controlled appropriately by the amplitude, width, and interval time of the pulses for implementing the neuromorphic systems.

Investigation of Deep Spiking Neural Networks Utilizing Gated Schottky Diode as Synaptic Devices.

Deep learning produces a remarkable performance in various applications such as image classification and speech recognition. However, state-of-the-art deep neural networks require a large number of weights and enormous computation power, which results in a bottleneck of efficiency for edge-device applications. To resolve these problems, deep spiking neural networks (DSNNs) have been proposed, given the specialized synapse and neuron hardware. In this work, the hardware neuromorphic system of DSNNs with gated Schottky diodes was investigated. Gated Schottky diodes have a near-linear conductance response, which can easily implement quantized weights in synaptic devices. Based on modeling of synaptic devices, two-layer fully connected neural networks are trained by off-chip learning. The adaptation of a neuron's threshold is proposed to reduce the accuracy degradation caused by the conversion from analog neural networks (ANNs) to event-driven DSNNs. Using left-justified rate coding as an input encoding method enables low-latency classification. The effect of device variation and noisy images to the classification accuracy is investigated. The time-to-first-spike (TTFS) scheme can significantly reduce power consumption by reducing the number of firing spikes compared to a max-firing scheme.

Compact SPICE Model of Memristor with Barrier Modulated Considering Short- and Long-Term Memory Characteristics by IGZO Oxygen Content.

This paper introduces a compact SPICE model of a two-terminal memory with a Pd/Ti/IGZO/p+-Si structure. In this paper, short- and long-term components are systematically separated and applied in each model. Such separations are conducted by the applied bias and oxygen flow rate (OFR) during indium gallium zinc oxide (IGZO) deposition. The short- and long-term components in the potentiation and depression curves are modeled by considering the process (OFR of IGZO) and bias conditions. The compact SPICE model with the physical mechanism of SiO2 modulation is introduced, which can be useful for optimizing the specification of memristor devices.

Effect of Post-Annealing on Barrier Modulations in Pd/IGZO/SiO2/p+-Si Memristors.

In this article, we study the post-annealing effect on the synaptic characteristics in Pd/IGZO/SiO2/p+-Si memristor devices. The O-H bond in IGZO films affects the switching characteristics that can be controlled by the annealing process. We propose a switching model based on using a native oxide as the Schottky barrier. The barrier height is extracted by the conduction mechanism of thermionic emission in samples with different annealing temperatures. Additionally, the change in conductance is explained by an energy band diagram including trap models. The activation energy is obtained by the depression curve of the samples with different annealing temperatures to better understand the switching mechanism. Moreover, our results reveal that the annealing temperature and retention can affect the linearity of potentiation and depression. Finally, we investigate the effect of the annealing temperature on the recognition rate of MNIST in the proposed neural network.

Ultrathin ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization.

Gaseous pollutants, including nitrogen oxides, pose a severe threat to ecosystems and human health; therefore, developing reliable gas-sensing systems to detect them is becoming increasingly important. Among the various options, metal-oxide-based gas sensors have attracted attention due to their capability for real-time monitoring and large response. In particular, in the field of materials science, there has been extensive research into controlling the morphological properties of metal oxides. However, these approaches have limitations in terms of controlling the response, sensitivity, and selectivity after the sensing material is deposited. In this study, we propose a novel method to improve the gas-sensing performance by utilizing the remnant polarization of ferroelectric thin-film transistor (FeTFT) gas sensors. The proposed FeTFT gas sensor has IGZO and HZO as the conducting channel and ferroelectric layer, respectively. It is demonstrated that the response and sensitivity of FeTFT gas sensors can be modulated by engineering the polarization of the ferroelectric layer. The amount of reaction sites in IGZO, including electrons and oxygen vacancy-induced negatively charged oxygen, is changed depending on upward and downward polarization. The results of this study provide an essential foundation for further development of gas sensors with tunable sensing properties.

Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy.

Recently, ferroelectric tunnel junctions (FTJs) have gained extensive attention as possible candidates for emerging memory and synaptic devices for neuromorphic computing. However, the working principles of FTJs remain controversial despite the importance of understanding them. In this study, we demonstrate a comprehensive and accurate analysis of the working principles of a metal-ferroelectric-dielectric-semiconductor stacked FTJ using low-frequency noise (LFN) spectroscopy. In contrast to resistive random access memory, the 1/f noise of the FTJ in the low-resistance state (LRS) is approximately two orders of magnitude larger than that in the high-resistance state (HRS), indicating that the conduction mechanism in each state differs significantly. Furthermore, the factors determining the conduction of the FTJ in each state are revealed through a systematic investigation under various conditions, such as varying the electrical bias, temperature, and bias stress. In addition, we propose an efficient method to decrease the LFN of the FTJ in both the LRS and HRS using high-pressure forming gas annealing.

Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Proposition of deposition and bias conditions for optimal signal-to-noise-ratio in resistor- and FET-type gas sensors.

In the field of gas sensor studies, most researchers are focusing on improving the response of the sensors to detect a low concentration of gas. However, factors that make a large response, such as abundant or strong adsorption sites, also work as a source of noise, resulting in a trade-off between response and noise. Thus, the response alone cannot fully evaluate the performance of sensors, and the signal-to-noise-ratio (SNR) should additionally be considered to design gas sensors with optimal performance. In this regard, thin-film-type sensing materials are good candidates thanks to their moderate response and noise level. In this paper, we investigate the effects of radio frequency (RF) sputtering power for deposition of sensing materials on the SNR of resistor- and field-effect transistor (FET)-type gas sensors fabricated on the same Si wafer. In the case of resistor-type gas sensors, the deposition conditions that improve the response also worsen the noise either by increasing the scattering at the bulk or damaging the interface of the sensing material. Among resistor-type gas sensors with sensing materials deposited with different RF powers, a sensor with low noise shows the largest SNR despite its small response. However, the noise of FET-type gas sensors is not affected by changes in RF power and thus there is no trade-off between response and noise. The results reveal different noise sources depending on the deposition conditions of the sensing material, and provide design guidelines for resistor- and FET-type gas sensors considering noise for optimal performance.

On-Chip Training Spiking Neural Networks Using Approximated Backpropagation With Analog Synaptic Devices.

Hardware-based spiking neural networks (SNNs) inspired by a biological nervous system are regarded as an innovative computing system with very low power consumption and massively parallel operation. To train SNNs with supervision, we propose an efficient on-chip training scheme approximating backpropagation algorithm suitable for hardware implementation. We show that the accuracy of the proposed scheme for SNNs is close to that of conventional artificial neural networks (ANNs) by using the stochastic characteristics of neurons. In a hardware configuration, gated Schottky diodes (GSDs) are used as synaptic devices, which have a saturated current with respect to the input voltage. We design the SNN system by using the proposed on-chip training scheme with the GSDs, which can update their conductance in parallel to speed up the overall system. The performance of the on-chip training SNN system is validated through MNIST data set classification based on network size and total time step. The SNN systems achieve accuracy of 97.83% with 1 hidden layer and 98.44% with 4 hidden layers in fully connected neural networks. We then evaluate the effect of non-linearity and asymmetry of conductance response for long-term potentiation (LTP) and long-term depression (LTD) on the performance of the on-chip training SNN system. In addition, the impact of device variations on the performance of the on-chip training SNN system is evaluated.

Pruning for Hardware-Based Deep Spiking Neural Networks Using Gated Schottky Diode as Synaptic Devices.

Deep learning represents state-of-the-art results in various machine learning tasks, but for applications that require real-time inference, the high computational cost of deep neural networks becomes a bottleneck for the efficiency. To overcome the high computational cost of deep neural networks, spiking neural networks (SNN) have been proposed. Herein, we propose a hardware implementation of the SNN with gated Schottky diodes as synaptic devices. In addition, we apply L1 regularization for connection pruning of the deep spiking neural networks using gated Schottky diodes as synap-tic devices. Applying L1 regularization eliminates the need for a re-training procedure because it prunes the weights based on the cost function. The compressed hardware-based SNN is energy efficient while achieving a classification accuracy of 97.85% which is comparable to 98.13% of the software deep neural networks (DNN).

Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells.

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth -0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth -0.5 to Vth+1.

Implementation of Synaptic Device Using Various High-k Gate Dielectric Stacks.

We investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based fieldeffect transistor (FET)-type memory device. An Al2O3/HfO2/Si3N4/SiO2 gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si3N4 and HfO2 layers are designed to charge trap layer for synaptic device. The mechanism of STP and LTP operation is analyzed by considering the device response to the potentiation and depression pulses and retention measurement of the memory functionality. To investigate the STP operation, paired pulse facilitation (PPF) measurement is performed. The retention characteristic is also studied to validate the LTP property of the device. By investigating a device with an Al2O3/HfO2/Si3N4 stack as a control device, it is shown that the Al2O3/HfO2/Si3N4/SiO2 stack device is suitable for a synaptic device in neuromorphic systems.

Gated Schottky Diode-Type Synaptic Device with a Field-Plate Structure to Reduce the Forward Current.

A gated Schottky diode with a field-plate structure is proposed and investigated as a new low-power synaptic device to suppress the forward current of the Schottky diode. In a hardware-based neural network, unwanted forward current can flow through gated Schottky diode-type synaptic devices during integration operations, possibly causing a malfunction of the neural network and increasing the power consumption. By adopting a field-plate structure, a virtual pn junction to suppress the forward current of the Schottky diode is formed in the poly-Si active layer. As a result, the unwanted forward current of the gated Schottky diode is successfully reduced to less than 1 pA/µm.