Programming memristor arrays with arbitrarily high precision for analog computing.

In-memory computing represents an effective method for modeling complex physical systems that are typically challenging for conventional computing architectures but has been hindered by issues such as reading noise and writing variability that restrict scalability, accuracy, and precision in high-performance computations. We propose and demonstrate a circuit architecture and programming protocol that converts the analog computing result to digital at the last step and enables low-precision analog devices to perform high-precision computing. We use a weighted sum of multiple devices to represent one number, in which subsequently programmed devices are used to compensate for preceding programming errors. With a memristor system-on-chip, we experimentally demonstrate high-precision solutions for multiple scientific computing tasks while maintaining a substantial power efficiency advantage over conventional digital approaches.

Reservoir computing using dynamic memristors for temporal information processing.

Reservoir computing systems utilize dynamic reservoirs having short-term memory to project features from the temporal inputs into a high-dimensional feature space. A readout function layer can then effectively analyze the projected features for tasks, such as classification and time-series analysis. The system can efficiently compute complex and temporal data with low-training cost, since only the readout function needs to be trained. Here we experimentally implement a reservoir computing system using a dynamic memristor array. We show that the internal ionic dynamic processes of memristors allow the memristor-based reservoir to directly process information in the temporal domain, and demonstrate that even a small hardware system with only 88 memristors can already be used for tasks, such as handwritten digit recognition. The system is also used to experimentally solve a second-order nonlinear task, and can successfully predict the expected output without knowing the form of the original dynamic transfer function.

Sparse coding with memristor networks.

Sparse representation of information provides a powerful means to perform feature extraction on high-dimensional data and is of broad interest for applications in signal processing, computer vision, object recognition and neurobiology. Sparse coding is also believed to be a key mechanism by which biological neural systems can efficiently process a large amount of complex sensory data while consuming very little power. Here, we report the experimental implementation of sparse coding algorithms in a bio-inspired approach using a 32 × 32 crossbar array of analog memristors. This network enables efficient implementation of pattern matching and lateral neuron inhibition and allows input data to be sparsely encoded using neuron activities and stored dictionary elements. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, we also perform natural image processing based on a learned dictionary.

Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor.

Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 µA/µm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.