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1.
Materials (Basel) ; 16(9)2023 Apr 23.
Artigo em Inglês | MEDLINE | ID: mdl-37176188

RESUMO

In this work, we investigate the ferroelectricity of stacked zirconium oxide and hafnium oxide (stacked HfZrO) with different thickness ratios under metal gate stress and simultaneously evaluate the electrical reliability of stacked ferroelectric films. Based on experimental results, we find that the stacked HfZrO films not only exhibited excellent ferroelectricity but also demonstrated a high performance on reliability. The optimized condition of the 45% Zr proportion exhibited a robust ferroelectric polarization value of 32.57 µC/cm2, and a polarization current with a peak value of 159.98 µA. Besides this, the ferroelectric stacked HfZrO also demonstrated good reliability with a ten-year lifetime under >-2 V constant voltage stress. Therefore, the appropriate modulation of zirconium proportion in stacked HfZrO showed great promise for integrating in high-performance ferroelectric memory.

2.
J Nanosci Nanotechnol ; 19(12): 7916-7919, 2019 Dec 01.
Artigo em Inglês | MEDLINE | ID: mdl-31196309

RESUMO

Optimal device integrity was achieved in Ni/SiGeOx/TiOy/TaN resistive memory by using a forming-free switch with a low switching power of 790 µW, stable endurance of 104 cycles, optimal retention time of 105 s, resistance window of at least 1150×, and tight current distributions at 85 °C. These characteristics are attributed to the low current switching obtained using SiGeOx with a high oxygen vacancy density and highly defective TiOy grain boundaries.

3.
J Nanosci Nanotechnol ; 15(4): 2810-3, 2015 Apr.
Artigo em Inglês | MEDLINE | ID: mdl-26353497

RESUMO

We report a low-temperature InP p-MOS with a high capacitance density of 2.7 µF/cm2, low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.

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