RESUMO
Two-dimensional (2D) semiconductor field-effect film transistors combine large carrier mobility with mechanical flexibility and therefore can be ideally suitable for wearable electronics or at the sensor interfaces of smart sensor systems. However, such applications require large-area solution processing as opposed to single-flake devices, where the critical challenge to overcome is the high interflake resistance values. In this report, using a narrow-channel, near-vertical transport device architecture, we have fabricated inkjet-printed sub-20 nm channel electrolyte-gated transistors with predominantly intraflake carrier transport. Therefore, the electronics transport in these transistors is not dominated by the high interflake resistance, and the intraflake material properties including doping density, defect concentration, contact resistance, and threshold voltage modulation can be examined and optimized independently to achieve a current density as high as 280 µA·µm-1. In addition, through the passivation of the sulfur vacancies with a tailored surface treatment, we demonstrate an impressive On-Off current ratio exceeding 1 × 107, complemented by a low subthreshold swing of 100 mV·decade-1. Next, exploiting these high-performance transistors, unipolar depletion-load-type inverters have been fabricated that show a maximum gain of 31. Furthermore, we have realized NAND, NOR, and OR gates, demonstrating their seamless operation at a frequency of 1 kHz. Therefore, this work represents an important step forward to realize electronic circuits based on printed 2D thin film transistors.
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The switching of conventional field-effect transistors (FETs) is limited by the Boltzmann barrier of thermionic emission, which prevents the realization of low-power electronics. In order to overcome this limitation, among others, unconventional device geometry with a ferroelectric/dielectric insulator stack has been proposed to demonstrate stable negative-capacitance behavior. Here, the switching of the ferroelectric layer behaves like a step-up amplifier and results in a body factor less than 1. This implies a larger change in the semiconductor surface potential compared to the applied gate voltage variation. The transistors with such ferroelectric/dielectric stack are known as negative-capacitance field-effect transistors (nc-FETs), and can demonstrate a subthreshold slope lower than the Boltzmann's limit (60 mV/decade). While nc-FETs have typically been realized with high-vacuum-deposition processes, here we show fully printed nc-FETs with amorphous indium-gallium-zinc oxide (a-IGZO) as the semiconductor material, Al2O3 as the dielectric, and poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as the polymer ferroelectric. The printed nc-FETs demonstrate an extremely low subthreshold slope of â¼2.3 mV/decade at room temperature, which remains below the Boltzmann's limit for over 5 orders of magnitude of drain currents. Furthermore, the unipolar depletion-load-type inverters fabricated using n-type nc-FETs have demonstrated an extraordinary signal gain of 2691.
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The major limitations of solution-processed oxide electronics include high process temperatures and the absence of necessary strain tolerance that would be essential for flexible electronic applications. Here, a combination of low temperature (<100 °C) curable indium oxide nanoparticle ink and a conductive silver nanoink, which are used to fabricate fully-printed narrow-channel thin film transistors (TFTs) on polyethylene terephthalate (PET) substrates, is proposed. The metal ink is printed onto the In2 O3 nanoparticulate channel to narrow the effective channel lengths down to the thickness of the In2 O3 layer and thereby obtain near-vertical transport across the semiconductor layer. The TFTs thus prepared show On/Off ratio ≈106 and simultaneous maximum current density of 172 µA µm-1 . Next, the depletion-load inverters fabricated on PET substrates demonstrate signal gain >200 and operation frequency >300 kHz at low operation voltage of VDD = 2 V. In addition, the near-vertical transport across the semiconductor layer is found to be largely strain tolerant with insignificant change in the TFT and inverter performance observed under bending fatigue tests performed down to a bending radius of 1.5 mm, which translates to a strain value of 5%. The devices are also found to be robust against atmospheric exposure when remeasured after a month.
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2D semiconductors, such as transition metal dichalcogenides (TMDs) show a rare combination of physical properties that include a large-enough bandgap to ensure sufficient current modulation in transistors, matching electron and hole mobility for complimentary logic operation, and sufficient mechanical flexibility of the nanosheets. Moreover, the solvent-exfoliated TMD-nanosheets may also be processed at low temperatures and onto a wide variety of substrates. However, the poor inter-flake transport in solution-cast 2D-TMD network transistors hinders the realization of high device mobility and current modulations that the intraflake transistors can regularly demonstrate. In this regard, fully printed and electrolyte-gated, narrow-channel MoS2 field-effect transistors (FETs) with simultaneous high current saturation (>310 µA µm-1 ) and on-off ratio (>106 ) are proposed here. The transport limitation is overcome by printing an additional metal layer onto the 2D-TMD nanosheet channel, which substantially shortens the effective channel lengths and results in predominant intraflake transport. In addition, a channel-capacitance-modulation induced subthermionic transport is recorded, which leads to a subthreshold slope value as low as 7.5 mV dec-1 . On the other hand, thermionic MOSFETs and fully printed depletion-mode NMOS inverters are also presented. The demonstrated generic approach involving chemically exfoliated nanosheet inks and the absolute device yield indicates the feasibility of fully printed 2D-TMD electronics.
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Printed sensors are among the most successful groups of devices within the domain of printed electronics, both in terms of their application versatility and the emerging market share. However, reports on fully printed gas sensors are rare in the literature, even though it can be an important development toward fully printed multisensor platforms for diagnostics, process control, and environmental safety-related applications. In this regard, here, we present the traditional tin oxide-based completely inkjet-printed co-continuous and mesoporous thin films with an extremely large surface-to-volume ratio and then investigate their NO2 sensing properties at low temperatures. A method known as evaporation-induced self-assembly (EISA) has been mimicked in this study using pluronic F127 (PEO106-PPO70-PEO106) as the soft templating agent and xylene as the micelle expander to obtain highly reproducible and spatially homogeneous co-continuous mesoporous crystalline SnO2 with an average pore diameter of the order of 15-20 nm. The fully printed SnO2 gas sensors thus produced show high linearity for NO2 detection, along with extremely high average response of 11,507 at 5 ppm NO2. On the other hand, the sensors show an ultralow detection limit of the order of 20 ppb with an easy to amplify response of 31. While the excellent electronic transport properties along such co-continuous, mesoporous structures are ensured by their well-connected (co-continuous) ligaments and pores (thereby ensuring high surface area and high mobility transport at the same time) and may actually be responsible for the outstanding sensor performance that has been observed, the use of an industrial printing technique ascertains the possibility of high-throughput manufacturing of such sensor units toward inexpensive and wide-range applications.
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Limited printing resolution has always been a major hindrance for printed electronics; irrespective of the high mobility demonstrated by solution-processed semiconductors, long-channel printed field-effect transistors (FETs) have demonstrated low On-state conductance and switching speeds. Although various concepts have been proposed to obtain narrow-channel printed FETs, the actual demonstration of high On-currents/channel conductance has been rare. In this context, herein, we report a general recipe to print co-continuous mesoporous structures with high surface-to-volume ratios for the first time for a large range of metallic and semiconducting oxides, both n- and p-type; next, by exploiting an innovative transistor architecture by printing an additional silver layer on top of the printed porous channel, we reduced the necessary length of electronic transport through the semiconductor material to a short vertical distance of the order of a few tens of nanometres. Basically, when a composite solid polymer electrolyte was used as a gate insulator, we essentially obtained channel length-independent transport with the unprecedented On-current of 67 µA µm-1 and transconductance of 143 µS µm-1 at the supply voltage of only 0.5 V. Among others, one may foresee the usage of these devices in high power switches and for drawing power from batteries in all-printed electronic circuits.
RESUMO
In semiconductor technology, the crystallite size of semiconductors is often directly correlated with their superior intrinsic and device mobility. However, when solution-processed, large crystals may bring in higher surface roughness and layer inhomogeneity, which can deteriorate the interface quality and device performance. Along this line, a thorough study on printed oxide field-effect transistors (FETs) has been performed, where the relative significance of crystallite size, surface roughness and spatial homogeneity are evaluated. The comprehensive investigations suggest the spatial homogeneity to be more important than crystallite size in solution processed/printed devices. It is demonstrated that the addition of a small amount of high boiling point polyol in the precursor ink can create large nucleation sites, resulting in reduced average crystallite size, superior inter-particle neck formation, and high spatial homogeneity. Interestingly, carefully estimated device mobility of these polyol-derived In2O3 FETs (â¼50-55 cm2 V-1 s-1) is found to be larger than the FETs prepared without polyols, although the crystallite size of the former is an order of magnitude smaller. The high spatial homogeneity and the large mobility values of the polyol-derived In2O3 transistors, as compared to the amorphous oxide FETs, lowers the importance of the latter, at least within the solution-processed/printed electronics domain.
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Following the ever-expanding technological demands, printed electronics has shown palpable potential to create new and commercially viable technologies that will benefit from its unique characteristics, such as, large-area and wide range of substrate compatibility, conformability and low-cost. Through the last few decades, printed/solution-processed field-effect transistors (FETs) and circuits have witnessed immense research efforts, technological growth and increased commercial interests. Although printing of functional inks comprising organic semiconductors has already been initiated in early 1990s, gradually the attention, at least partially, has been shifted to various forms of inorganic semiconductors, starting from metal chalcogenides, oxides, carbon nanotubes and very recently to graphene and other 2D semiconductors. In this review, the entire domain of printable inorganic semiconductors is considered. In fact, thanks to the continuous development of materials/functional inks and novel design/printing strategies, the inorganic printed semiconductor-based circuits today have reached an operation frequency up to several hundreds of kilohertz with only a few nanosecond time delays at the individual FET/inverter levels; in this regard, often circuits based on hybrid material systems have been found to be advantageous. At the end, a comparison of relative successes of various printable inorganic semiconductor materials, the remaining challenges and the available future opportunities are summarized.
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Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes, and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO)-based-diffused a-IGZO-ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping-mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS-based logic circuits have also been demonstrated toward new-generation portable electronics.
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Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV-visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.
RESUMO
Electric field tuning of magnetism is one of the most intensely pursued research topics of recent times aiming at the development of new-generation low-power spintronics and microelectronics. However, a reversible magnetoelectric effect with an on/off ratio suitable for easy and precise device operation is yet to be achieved. Here we propose a novel route to robustly tune magnetism via the charging/discharging processes of hybrid supercapacitors, which involve electrostatic (electric-double-layer capacitance) and electrochemical (pseudocapacitance) doping. We use both charging mechanisms-occurring at the La0.74Sr0.26MnO3/ionic liquid interface to control the balance between ferromagnetic and non-ferromagnetic phases of La1-xSrxMnO3 to an unprecedented extent. A magnetic modulation of up to ≈33% is reached above room temperature when applying an external potential of only about 2.0 V. Our case study intends to draw attention to new, reversible physico-chemical phenomena in the rather unexplored area of magnetoelectric supercapacitors.
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A printed vertical field-effect transistor is demonstrated, which decouples critical device dimensions from printing resolution. A printed mesoporous semiconductor layer, sandwiched between vertically stacked drive electrodes, provides <50 nm channel lengths. A polymer-electrolyte-based gate insulator infiltrates the percolating pores of the mesoporous channel to accumulate charge carriers at every semiconductor domain, thereby, resulting in an unprecedented current density of MA cm-2 .
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Printable, physical, and air-stable composite solid polymer electrolytes (CSPEs) with high ionic conductivity have been established as a suitable alternative to standard dielectric gate insulators for printed field-effect transistors (FETs) and logics. We have performed a stress and temperature stability study involving several CSPEs. Mechanical tensile and shear tests have been performed to determine the physical condition of CSPEs. A comprehensive temperature dependent study has been conducted within the working temperature range which electric double layer (EDL) capacitors or CSPE-gated FETs may typically experience during their lifetime. Moreover, calorimetric measurements have been performed to investigate the CSPEs stability, especially at low temperatures. Mechanical characterizations have shown tensile strength and shear modulus of the material that is typical for solid polymer electrolytes while DSC measurements show no change in the physical state within the measured temperature range. An expected increase in ionic conductivity of the CSPEs of nearly 1 order of magnitude has been observed with an increase in temperature, while an anomalous positive temperature relationship to EDL capacitance has also been noticed. Interestingly, the transistor performance characteristics, namely, on-current and threshold voltage, are found to be quite independent of the temperature, thus ensuring a large and stable operation temperature window for CSPE-gated FETs. The other parameters, subthreshold slope and the device mobility, have varied following the classical semiconductor behavior. In fact, the present study not only provides a detailed understanding of temperature dependence of the CSPE-gated FETs but also offers an insight into the physical and electrical properties of the CSPEs itself. Therefore, these results may very well help to comprehend and improve EDL capacitors, supercapacitors, and other devices that use CSPEs as the active material.
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Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm(2) V(-1) s(-1).
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Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation.
RESUMO
Critical prerequisites for solution-processed/printed field-effect transistors (FETs) and logics are excellent electrical performance including high charge carrier mobility, reliability, high environmental stability and low/preferably room temperature processing. Oxide semiconductors can often fulfill all the above criteria, sometimes even with better promise than their organic counterparts, except for their high process temperature requirement. The need for high annealing/curing temperatures renders oxide FETs rather incompatible to inexpensive, flexible substrates, which are commonly used for high-throughput and roll-to-roll additive manufacturing techniques, such as printing. To overcome this serious limitation, here we demonstrate an alternative approach that enables completely room-temperature processing of printed oxide FETs with device mobility as large as 12.5 cm(2)/(V s). The key aspect of the present concept is a chemically controlled curing process of the printed nanoparticle ink that provides surprisingly dense thin films and excellent interparticle electrical contacts. In order to demonstrate the versatility of this approach, both n-type (In2O3) and p-type (Cu2O) oxide semiconductor nanoparticle dispersions are prepared to fabricate, inkjet printed and completely room temperature processed, all-oxide complementary metal oxide semiconductor (CMOS) invertors that can display significant signal gain (â¼18) at a supply voltage of only 1.5 V.
RESUMO
An extension in magnetoelectric effects is proposed to include reversible chemistry-controlled magnetization variations. This ion-intercalation-driven magnetic control can be fully reversible and pertinent to bulk material volumes. The concept is demonstrated for ferromagnetic iron oxide where the intercalated lithium ions cause valence change and partial redistribution of Fe(3+) cations yielding a large and fully reversible change in magnetization at room temperature.
Assuntos
Fenômenos Magnéticos , Imãs/química , Compostos Férricos/química , Espectroscopia de Mossbauer , Relação Estrutura-AtividadeRESUMO
Inkjet printed and low voltage (≤1 V) driven field-effect transistors (FETs) are prepared from precursor-made In2O3 as the transistor channel and a composite solid polymer electrolyte (CSPE) as the gate dielectric. Printed halide precursors are annealed at different temperatures (300-500 °C); however, the devices that are heated to 400 °C demonstrate the best electrical performance including field-effect mobility as high as 126 cm(2) V(-1) s(-1) and subthreshold slope (68 mV/dec) close to the theoretical limit. These outstanding device characteristics in combination with ease of fabrication, moderate annealing temperatures and low voltage operation comprise an attractive set of parameters for battery compatible and portable electronics.
RESUMO
Printed electronics (PE) represents any electronic devices, components or circuits that can be processed using modern-day printing techniques. Field-effect transistors (FETs) and logics are being printed with intended applications requiring simple circuitry on large, flexible (e.g., polymer) substrates for low-cost and disposable electronics. Although organic materials have commonly been chosen for their easy printability and low temperature processability, high quality inorganic oxide-semiconductors are also being considered recently. The intrinsic mobility of the inorganic semiconductors are always by far superior than the organic ones; however, the commonly expressed reservations against the inorganic-based printed electronics are due to major issues, such as high processing temperatures and their incompatibility with solution-processing. Here we show a possibility to circumvent these difficulties and demonstrate a room-temperature processed and inkjet printed inorganic-oxide FET where the transistor channel is composed of an interconnected nanoparticle network and a solid polymer electrolyte serves as the dielectric. Even an extremely conservative estimation of the field-effect mobility of such a device yields a value of 0.8 cm(2)/(V s), which is still exceptionally large for a room temperature processed and printed transistor from inorganic materials.