Highly Efficient Photon Energy Conversion and Ultrasensitive Self-Powered Photodetection via a Monolithic p-3C-SiC Nanothin Film on p-Si/n-Si Double Junction.

The pursuit of increased efficiency of photoelectric energy conversion through optimized semiconductor structures remains highly competitive, with current results yet to align with broad expectations. In this study, we discover a significant enhancement in photocurrent performance of a p-3C-SiC nanothin film on p-Si/n-Si double junction (DJ) heterostructure that integrates p-3C-SiC/p-Si heterojunction and p-Si/n-Si homojunction. The vertical photocurrent (VPC) and vertical photoresponsivity exhibit a substantial enhancement in the DJ heterostructure, surpassing by a maximum of 43-fold compared to the p-3C-SiC/n-Si single junction (SJ) counterpart. The p-3C-SiC layer and n-Si substrate of the two heterostructures have similar material and geometrical properties. More importantly, the fabrication costs for the DJ and SJ heterostructure devices are comparable. Our results demonstrate a significant potential for using DJ devices in energy harvesters, micro/nano electromechanical systems, and sensing applications. This research may also lead to the creation of advanced optoelectronic devices using DJ structures, where employing various semiconductor materials to achieve exceptional performance through the application of the concept and theoretical model described in this work.

The effect of wafer thinning and thermal capacitance on chip temperature of SiC Schottky diodes during surge currents.

Due to superior material properties of SiC for high-voltage devices, SiC Schottky diodes are used in energy-conversion systems such as solar-cell inverters, battery chargers, and power modules for electric cars and unmanned aerial vehicles. The reliable operation of these systems requires the chip temperature of SiC Schottky diodes to be maintained within the limit set by the device package. This is especially crucial during surge-current events that dissipate heat within the device. As a thermal-management method, manufactures of commercial SiC Schottky diodes have introduced wafer thinning practices to reduce the thickness of the SiC chip and, consequently, to reduce its thermal resistance. However, this also leads to a reduction in the thermal capacitance. In this paper, we present experimental data and theoretical analysis to demonstrate that the reduced thermal capacitance has a much larger adverse effect in comparison to the beneficial reduction of the thermal resistance. An implication of the presented results is that, contrary to the adopted wafer thinning practices, SiC Schottky diodes fabricated without wafer thinning have superior surge-current capability.

Quantified density of performance-degrading near-interface traps in SiC MOSFETs.

Characterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.

Description and Verification of the Fundamental Current Mechanisms in Silicon Carbide Schottky Barrier Diodes.

Attempts to model the current through Schottky barrier diodes using the two fundamental mechanisms of thermionic emission and tunnelling are adversely impacted by defects and second order effects. This has led to the publication of countless different models to account for these effects, including some with non-physical parameters. Recently, we have developed silicon carbide Schottky barrier diodes that do not suffer from second order effects, such as excessive leakage, carrier generation and recombination, and non-uniform barrier height. In this paper, we derive the foundational current equations to establish clear links between the fundamental current mechanisms and the governing parameters. Comparing these equations with measured current-voltage characteristics, we show that the fundamental equations for tunnelling and thermionic emission can accurately model 4H silicon carbide Schottky barrier diodes over a large temperature and voltage range. Based on the obtained results, we discuss implications and misconceptions regarding barrier inhomogeneity, barrier height measurement, and reverse-bias temperature dependencies.

Highly sensitive p-type 4H-SiC van der Pauw sensor.

This paper presents for the first time a p-type 4H silicon carbide (4H-SiC) van der Pauw strain sensor by utilizing the strain induced effect in four-terminal devices. The sensor was fabricated from a 4H-SiC (0001) wafer, using a 1 µm thick p-type epilayer with a concentration of 1018 cm-3. Taking advantage of the four-terminal configuration, the sensor can eliminate the need for resistance-to-voltage conversion which is typically required for two-terminal devices. The van der Pauw sensor also exhibits an excellent repeatability and linearity with a significantly large output voltage in induced strain ranging from 0 to 334 ppm. Various sensors aligned in different orientations were measured and a high sensitivity of 26.3 ppm-1 was obtained. Combining these performances with the excellent mechanical strength, electrical conductivity, thermal stability, and chemical inertness of 4H-SiC, the proposed sensor is promising for strain monitoring in harsh environments.

Excellent Rectifying Properties of the n-3C-SiC/p-Si Heterojunction Subjected to High Temperature Annealing for Electronics, MEMS, and LED Applications.

This work examines the stability of epitaxial 3C-SiC/Si heterojunctions subjected to heat treatments between 1000 °C and 1300 °C. Because of the potential for silicon carbide in high temperature and harsh environment applications, and the economic advantages of growing the 3C-SiC polytype on large diameter silicon wafers, its stability after high temperature processing is an important consideration. Yet recently, this has been thrown into question by claims that the heterojunction suffers catastrophic degradation at temperatures above 1000 °C. Here we present results showing that the heterojunction maintains excellent diode characteristics following heat treatment up to 1100 °C and while some changes were observed between 1100 °C and 1300 °C, diodes maintained their rectifying characteristics, enabling compatibility with a large range of device fabrication. The parameters of as-grown diodes were J0 = 1 × 10-11 A/mm2, n = 1.02, and +/-2V rectification ratio of 9 × 106. Capacitance and thermal current-voltage analysis was used to characterize the excess current leakage mechanism. The change in diode characteristics depends on diode area, with larger areas (1 mm2) having reduced rectification ratio while smaller areas (0.04 mm2) maintained excellent characteristics of J0 = 2 × 10-10 A/mm2, n = 1.28, and +/-2V ratio of 3 × 106. This points to localized defect regions degrading after heat treatment rather than a fundamental issue of the heterojunction.

Piezoresistive effect in p-type 3C-SiC at high temperatures characterized using Joule heating.

Cubic silicon carbide is a promising material for Micro Electro Mechanical Systems (MEMS) applications in harsh environ-ments and bioapplications thanks to its large band gap, chemical inertness, excellent corrosion tolerance and capability of growth on a Si substrate. This paper reports the piezoresistive effect of p-type single crystalline 3C-SiC characterized at high temperatures, using an in situ measurement method. The experimental results show that the highly doped p-type 3C-SiC possesses a relatively stable gauge factor of approximately 25 to 28 at temperatures varying from 300 K to 573 K. The in situ method proposed in this study also demonstrated that, the combination of the piezoresistive and thermoresistive effects can increase the gauge factor of p-type 3C-SiC to approximately 20% at 573 K. The increase in gauge factor based on the combination of these phenomena could enhance the sensitivity of SiC based MEMS mechanical sensors.

Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer.

Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm(2) above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers.

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 µm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

Influence of various plasma treatment on the properties of carbon nanotubes for composite applications.

In present work, the effects of hydrogen and oxygen plasma treatments on the structural properties of carbon nanotubes (CNTs) synthesized by catalytic CVD (Chemical Vapor Deposition) have been systematically investigated. Field emission scanning electron microscopy (FE-SEM), high-resolution transmission electron microscopy (HRTEM), and Raman spectroscopy were used to characterize the microstructural changes of the CNTs. The oxygen plasma treatment resulted in that the nanoparticles were appeared at the surface of CNTs. At high r.f. power (300 Watt), the microstructure of CNT was changed from nanotube type to nano particles. Long plasma treatment time changed the CNT morphology dramatically. For hydrogen plasma, however, there was no change in microstructure of CNT From the Raman analysis, the crystallinity of CNT was deteriorated by the plasma treatment, regardless of plasma power, treatment time, and gas types. The CNTs treated in oxygen plasma for 90 min showed excellent dispersion properties in aqueous solution.