Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application.

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design.

Ferroelectric-defined reconfigurable homojunctions for in-memory sensing and computing.

Recently, the increasing demand for data-centric applications is driving the elimination of image sensing, memory and computing unit interface, thus promising for latency- and energy-strict applications. Although dedicated electronic hardware has inspired the development of in-memory computing and in-sensor computing, folding the entire signal chain into one device remains challenging. Here an in-memory sensing and computing architecture is demonstrated using ferroelectric-defined reconfigurable two-dimensional photodiode arrays. High-level cognitive computing is realized based on the multiplications of light power and photoresponsivity through the photocurrent generation process and Kirchhoff's law. The weight is stored and programmed locally by the ferroelectric domains, enabling 51 (>5 bit) distinguishable weight states with linear, symmetric and reversible manipulation characteristics. Image recognition can be performed without any external memory and computing units. The three-in-one paradigm, integrating high-level computing, weight memorization and high-performance sensing, paves the way for a computing architecture with low energy consumption, low latency and reduced hardware overhead.

Simulation of a Fully Digital Computing-in-Memory for Non-Volatile Memory for Artificial Intelligence Edge Applications.

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation scheme for machine learning applications. When applied to a modified ResNet18 network trained under the CIFAR-10 dataset, the simulations indicate that the proposed CCLUTM-based DNV-CIM can achieve a peak energy efficiency of 75.18 TOPS/W with 4-bit multiplication and accumulation (MAC) operations.

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection.

This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.

Reflow Soldering Capability Improvement by Utilizing TaN Interfacial Layer in 1Mbit RRAM Chip.

We investigated the thermal stability of a 1Mbit OxRRAM array embedded in 28 nm COMS technology. A back-end-of-line (BEOL) solution with a TaN-Ta interfacial layer was proposed to eliminate the failure rate after reflow soldering assembly at 260 °C. By utilizing a TaN-Ta interfacial layer (IL), the oxygen defects in conductive filament were redistributed, and electromigration lifetimes of Cu-based damascene interconnects were improved, which contributed to optimization. This work provides a potential solution for the practical application of embedded RRAM beyond the 28 nm technology node.

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array.

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system's operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.

Ultra-High Performance Amorphous Ga2 O3 Photodetector Arrays for Solar-Blind Imaging.

The growing demand for scalable solar-blind image sensors with remarkable photosensitive properties has stimulated the research on more advanced solar-blind photodetector (SBPD) arrays. In this work, the authors demonstrate ultrahigh-performance metal-semiconductor-metal (MSM) SBPDs based on amorphous (a-) Ga2 O3 via a post-annealing process. The post-annealed MSM a-Ga2 O3 SBPDs exhibit superhigh sensitivity of 733 A/W and high response speed of 18 ms, giving a high gain-bandwidth product over 104 at 5 V. The SBPDs also show ultrahigh photo-to-dark current ratio of 3.9 × 107 . Additionally, the PDs demonstrate super-high specific detectivity of 3.9 × 1016 Jones owing to the extremely low noise down to 3.5 fW Hz-1/2 , suggesting high signal-to-noise ratio. Underlying mechanism for such superior photoelectric properties is revealed by Kelvin probe force microscopy and first principles calculation. Furthermore, for the first time, a large-scale, high-uniformity 32 × 32 image sensor array based on the post-annealed a-Ga2 O3 SBPDs is fabricated. Clear image of target object with high contrast can be obtained thanks to the high sensitivity and uniformity of the array. These results demonstrate the feasibility and practicality of the Ga2 O3 PDs for applications in solar-blind imaging, environmental monitoring, artificial intelligence and machine vision.

Suppression of Filament Overgrowth in Conductive Bridge Random Access Memory by Ta2O5/TaOx Bi-Layer Structure.

Bi-layer structure has been widely adopted to improve the reliability of the conductive bridge random access memory (CBRAM). In this work, we proposed a convenient and economical solution to achieve a Ta2O5/TaOx bi-layer structure by using a low-temperature annealing process. The addition of a TaOx layer acted as an external resistance suppressing the overflow current during set programming, thus achieving the self-compliance switching. As a result, the distributions of high-resistance states and low-resistance states are improved due to the suppression of the overset phenomenon. In addition, the LRS retention of the CBRAM is obviously enhanced due to the recovery of defects in the switching film. This work provides a simple and economical method to improve the reliability of CBRAM.