P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Nanoscale Channel Length MoS2 Vertical Field-Effect Transistor Arrays with Side-Wall Source/Drain Electrodes.

Two-dimensional transition metal dichalcogenides (TMDCs) have natural advantages in overcoming the short-channel effect in field-effect transistors (FETs) and in fabricating three-dimensional FETs, which benefit in increasing device density. However, so far, most reported works related to MoS2 FETs with a sub-100 nm channel employ mechanically exfoliated materials and all of the works involve electron beam lithography (EBL), which may limit their application in fabricating wafer-scale device arrays as demanded in integrated circuits (ICs). In this work, MoS2 FET arrays with a side-wall source and drain electrodes vertically distributed are designed and fabricated. The channel length of the as-fabricated FET is basically determined by the thickness of an insulating layer between the source and drain electrodes. The vertically distributed source and drain electrodes enable to reduce the electrode-occupied area and increase in the device density. The as-fabricated vertical FETs exhibit on/off ratios comparable to those of mechanically exfoliated MoS2 FETs with a nanoscale channel length under identical VDS. In addition, the as-fabricated FETs can work at a VDS as low as 10 mV with a desirable on/off ratio (1.9 × 107), which benefits in developing low-power devices. Moreover, the fabrication process is free from EBL and can be applied to wafer-scale device arrays. The statistical results show that the fabricated FET arrays have a device yield of 87.5% and an average on/off ratio of about 1.7 × 106 at a VDS of 10 mV, with the lowest and highest ones to be about 1.3 × 104 and 1.9 × 107, respectively, demonstrating the good reliability of our fabrication process. Our work promises a bright future for TMDCs in realizing high-density and low-power nanoelectronic devices in ICs.

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation.

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

High-Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD-Grown n-MoS2 and p-MoTe2.

In this work, monolithic three-dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large-scale n-MoS2 and p-MoTe2 grown by the chemical vapor deposition method. In the CMOS device, the n- and p-channel field-effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO2 is used as the gate dielectric. An Al2 O3 seed layer is used to protect the MoS2 from heavily n-doping in the later-on atomic layer deposition process. P-MoTe2 FET is intentionally designed as the upper layer. Because p-doping of MoTe2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe2 . An HfO2 capping layer is employed to further balance the transfer curves of n- and p-channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at VDD of 1 V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at VDD of 1 V. This work demonstrates the advantage of two-dimensional semi-conductive transition metal dichalcogenides in fabricating high-density integrated circuits.

Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2.

Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low power consumption. So far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. Besides, most of the inverters were made of mechanically exfoliated materials, which hinders their reproducible production and large-scale integration in practical application. In this study, we demonstrate a practical approach to fabricate CMOS inverter arrays using large-area p-MoTe2 and n-MoS2, which are grown via chemical vapor deposition method. The current characteristics of the channel materials are balanced by atomic layer depositing Al2O3. Complete logic swing and clear dynamic switching behavior are observed in the inverters. Especially, ultra-low power consumption of ∼0.37 nW is achieved. Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.

Atomic-Precision Repair of a Few-Layer 2H-MoTe2 Thin Film by Phase Transition and Recrystallization Induced by a Heterophase Interface.

2D semiconductors have emerged as promising candidates for post-silicon nanoelectronics, owing to their unique properties and atomic thickness. However, in the handling of 2D material, various forms of macroscopic damage, such as cracks, wrinkles, and scratches, etc., are usually introduced, which cause adverse effects on the material properties and device performance. Repairing such macroscopic damage is crucial for improving device performance and reliability, especially for large-scale 2D device arrays. Here, a method is demonstrated repair damage to few-layer 2H-MoTe2 films with atomic precision, and its mechanism is elucidated. The repaired 2H-MoTe2 inherits the lattice orientation of the adjacent original 2H-MoTe2 , thereby forming an atomically perfect lattice at the repaired interface. The time-evolution experiments show that the interface between the 2H- and early formed 1T'-MoTe2 plays an important role in the subsequent phase transition and recrystallization. Electrical measurements on the original MoTe2 , repaired MoTe2 , and cross-interface regions show unobservable differences, indicating that the repaired MoTe2 has the same electrical quality as the original one and the interface does not introduce extra scattering centers for carrier transport. The findings provide an effective strategy for macroscopic damage repair of few-layer 2H-MoTe2 , which paves the way for its practical application in advanced electronics and optoelectronics.

Consequence of Optimal Bonding on Disordered Structure and Improved Luminescence Properties in T-Phase (Ba,Ca)2SiO4:Eu2+ Phosphor.

T-phase (Ba,Ca)2SiO4:Eu2+, showing excellent luminescent thermal stability, has a positionally disordered structure with the splitting of five atom sites, but until now the reason has remained unclear. Herein, we investigate the coordination environments of each cation site in detail to understand the origins of the atom site splitting. We find that the three cation sites in the split-atom-site model are optimally bonded with ligand O atoms compared to the unsplit-atom-site model. This atom site splitting results in larger room and smaller room for each splitting cation site, which just accommodates larger Ba2+ ions and smaller Ca2+ ions, respectively, leading to more rigid structure. Based on the X-ray diffraction data refinement, the boundary of the T-phase for (Ba1- xCa x)2SiO4 is redetermined. The Eu2+-doped T-phase (Ba,Ca)2SiO4 phosphors show excellent luminescent thermal stability, which can be attributed to optimal bonding and more rigid structure with atom site splitting. These results indicate that T-phase (Ba,Ca)2SiO4:Eu2+ phosphors have promise for practical applications.

Control of Luminescence in Eu2+-Doped Orthosilicate-Orthophosphate Phosphors by Chainlike Polyhedra and Electronic Structures.

A series of Eu2+-doped orthosilicate-orthophosphate solid-solution phosphors, KxBa1.97-x(Si1-xPx)O4:0.03Eu2+, have been synthesized via the conventional solid-state reaction. Using varying compositions, the lowest-energy excitation can be tuned from 470 to 405 nm, with an emission from 515 to 423 nm. We determined how chainlike cation polyhedra controlled excitation- and emission-band features by introducing in-chain characteristic length d22 and outside-chain characteristic length d12 and that there was a nearly linear relationship between the lowest-energy-excitation position and the ratio of d22 to d12. This influence of chainlike polyhedra on luminescence can be understood through the inductive effect. Luminescent thermal properties are improved remarkably by the cosubstitution of K+ and P5+ ions for Ba2+ and Si4+ ions with a T1/2 over 200 °C. We have established the host-referred-binding-energy (HRBE) and vacuum-referred-binding-energy (VRBE) schemes for the electronic structure of the series of lanthanide-doped phosphors according to the Dorenbos model and given a thermal-quenching mechanism for this series of phosphors.