Calibration Methods for Time-to-Digital Converters.

In this paper, two of the most common calibration methods of synchronous TDCs, which are the bin-by-bin calibration and the average-bin-width calibration, are first presented and compared. Then, an innovative new robust calibration method for asynchronous TDCs is proposed and evaluated. Simulation results showed that: (i) For a synchronous TDC, the bin-by-bin calibration, applied to a histogram, does not improve the TDC's differential non-linearity (DNL); nevertheless, it improves its Integral Non-Linearity (INL), whereas the average-bin-width calibration significantly improves both the DNL and the INL. (ii) For an asynchronous TDC, the DNL can be improved up to 10 times by applying the bin-by-bin calibration, whereas the proposed method is almost independent of the non-linearity of the TDC and can improve the DNL up to 100 times. The simulation results were confirmed by experiments carried out using real TDCs implemented on a Cyclone V SoC-FPGA. For an asynchronous TDC, the proposed calibration method is 10 times better than the bin-by-bin method in terms of the DNL improvement.

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout.

The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.