Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth.

A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to date, the lack of dangling bonds on sp2 oriented graphene sheets has limited the high precursor nucleation density enabling atomic layer deposition of sub-1 nm EOT gate oxides. It is shown here that by deploying a low-temperature AlOx (LT AlOx) process, involving atomic layer deposition (ALD) of Al2O3 at 50 °C with a chemical vapor deposition (CVD) component, a high nucleation density layer can be formed, which templates the growth of a high-k dielectric, such as HfO2. Atomic force microscopy (AFM) imaging shows that at 50 °C, the Al2O3 spontaneously forms a pinhole-free, sub-2 nm layer on graphene. Density functional theory (DFT) based simulations indicate that the spreading out of AlOx clusters on the carbon surface enables conformal oxide deposition. Device applications of the LT AlOx deposition scheme were investigated through electrical measurements on metal oxide semiconductor capacitors (MOSCAPs) with Al2O3/HfO2 bilayer gate oxides using both standard Ti/Pt metal gates as well as TiN/Ti/Pd gettering gates. In this study, LT AlOx was used to nucleate HfO2 and it was shown that bilayer gate oxide stacks of 2.85 and 3.15 nm were able to achieve continuous coverage on carbon nanotubes (CNTs). The robustness of the bilayer was tested through deployment in a CNT-based field-effect transistor (FET) configuration with a gate leakage of less than 10-8 A/µm per CNT.

Atomically flat and uniform relaxed III-V epitaxial films on silicon substrate for heterogeneous and hybrid integration.

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.

Scanning tunneling microscopy/spectroscopy study of atomic and electronic structures of In2O on InAs and In0.53Ga0.47As(001)-(4×2) surfaces.

Interfacial bonding geometry and electronic structures of In(2)O on InAs and In(0.53)Ga(0.47)As(001)-(4×2) have been investigated by scanning tunneling microscopy/scanning tunneling spectroscopy (STM/STS). STM images show that the In(2)O forms an ordered monolayer on both InAs and InGaAs surfaces. In(2)O deposition on the InAs(001)-(4×2) surface does not displace any surface atoms during both room temperature deposition and postdeposition annealing. Oxygen atoms from In(2)O molecules bond with trough In/Ga atoms on the surface to form a new layer of O-In/Ga bonds, which restore many of the strained trough In/Ga atoms into more bulklike tetrahedral sp(3) bonding environments. STS reveals that for both p-type and n-type clean In(0.53)Ga(0.47)As(001)-(4×2) surfaces, the Fermi level resides near the valence band maximum (VBM); however, after In(2)O deposition and postdeposition annealings, the Fermi level position is close to the VBM for p-type samples and close to the conduction band minimum for n-type samples. This result indicates that In(2)O bonding eliminates surface states within the bandgap and forms an unpinned interface when bonding with In(0.53)Ga(0.47)As/InP(001)-(4×2). Density function theory is used to confirm the experimental finding.

Electronic properties of adsorbates on GaAs(001)-c(2x8)/(2x4).

A systematic experimental and theoretical study was performed to determine the causes of oxide-induced Fermi level pinning and unpinning on GaAs(001)-c(2 x 8)/(2 x 4). Scanning tunneling spectroscopy (STS) and density functional theory (DFT) were used to study four different adsorbates' (O(2), In(2)O, Ga(2)O, and SiO) bonding to the GaAs(001)-c(2 x 8)/(2 x 4) surface. The STS results revealed that out of the four adsorbates studied, only one left the Fermi level unpinned, Ga(2)O. DFT calculations were used to elucidate the causes of the Fermi level pinning. Two distinct pinning mechanisms were identified: direct (adsorbate induced states in the band gap region) and indirect pinnings (generation of undimerized As atoms). For O(2) dissociative chemisorption onto GaAs(001)-c(2 x 8)/(2 x 4), the Fermi level pinning was only indirect, while direct Fermi level pinning was observed when In(2)O was deposited on GaAs(001)-c(2 x 8)/(2 x 4). In the case of SiO on GaAs(001)-c(2 x 8)/(2 x 4), the Fermi level pinning was a combination of the two mechanisms.

Direct and indirect causes of Fermi level pinning at the SiO/GaAs interface.

The correlation between atomic bonding sites and the electronic structure of SiO on GaAs(001)-c(2x8)/(2x4) was investigated using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and density functional theory (DFT). At low coverage, STM images reveal that SiO molecules bond Si end down; this is consistent with Si being undercoordinated and O being fully coordinated in molecular SiO. At approximately 5% ML (monolayer) coverage, multiple bonding geometries were observed. To confirm the site assignments from STM images, DFT calculations were used to estimate the total adsorption energies of the different bonding geometries as a function of SiO coverage. STS measurements indicated that SiO pins the Fermi level midgap at approximately 5% ML coverage. DFT calculations reveal that the direct causes of Fermi level pinning at the SiO GaAs(001)-(2x4) interface are a result of either local charge buildups or the generation of partially filled dangling bonds on Si atoms.