Hardware implementation of a true random number generator integrating a hexagonal boron nitride memristor with a commercial microcontroller.

The development of the internet-of-things requires cheap, light, small and reliable true random number generator (TRNG) circuits to encrypt the data-generated by objects or humans-before transmitting them. However, all current solutions consume too much power and require a relatively large battery, hindering the integration of TRNG circuits on most objects. Here we fabricated a TRNG circuit by exploiting stable random telegraph noise (RTN) current signals produced by memristors made of two-dimensional (2D) multi-layered hexagonal boron nitride (h-BN) grown by chemical vapor deposition and coupled with inkjet-printed Ag electrodes. When biased at small constant voltages (≤70 mV), the Ag/h-BN/Ag memristors exhibit RTN signals with very low power consumption (∼5.25 nW) and a relatively high current on/off ratio (∼2) for long periods (>1 hour). We constructed TRNG circuits connecting an h-BN memristor to a small, light and cheap commercial microcontroller, producing a highly-stochastic, high-throughput signal (up to 7.8 Mbit s-1) even if the RTN at the input gets interrupted for long times up to 20 s, and if the stochasticity of the RTN signal is reduced. Our study presents the first full hardware implementation of 2D-material-based TRNGs, enabled by the unique stability and figures of merit of the RTN signals in h-BN based memristors.

A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules.

Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.

Standards for the Characterization of Endurance in Resistive Switching Devices.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing.

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

On the Modeling of the Donor/Acceptor Compensation Ratio in Carbon-Doped GaN to Univocally Reproduce Breakdown Voltage and Current Collapse in Lateral GaN Power HEMTs.

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. Due to the introduction of trap levels in the GaN bandgap, it is well known that these impurities give rise to dispersion, leading to the so-called "current collapse" as a collateral effect. Moreover, first-principles calculations and experimental evidence point out that C introduces trap levels of both acceptor and donor types. Here, we report on the modeling of the donor/acceptor compensation ratio (CR), that is, the ratio between the density of donors and acceptors associated with C doping, to consistently and univocally reproduce experimental breakdown voltage (VBD) and current-collapse magnitude (ΔICC). By means of calibrated numerical device simulations, we confirm that ΔICC is controlled by the effective trap concentration (i.e., the difference between the acceptor and donor densities), but we show that it is the total trap concentration (i.e., the sum of acceptor and donor densities) that determines VBD, such that a significant CR of at least 50% (depending on the technology) must be assumed to explain both phenomena quantitatively. The results presented in this work contribute to clarifying several previous reports, and are helpful to device engineers interested in modeling C-doped lateral GaN power HEMTs.

Advanced Data Encryption ​using 2D Materials.

Advanced data encryption requires the use of true random number generators (TRNGs) to produce unpredictable sequences of bits. TRNG circuits with high degree of randomness and low power consumption may be fabricated by using the random telegraph noise (RTN) current signals produced by polarized metal/insulator/metal (MIM) devices as entropy source. However, the RTN signals produced by MIM devices made of traditional insulators, i.e., transition metal oxides like HfO2 and Al2 O3 , are not stable enough due to the formation and lateral expansion of defect clusters, resulting in undesired current fluctuations and the disappearance of the RTN effect. Here, the fabrication of highly stable TRNG circuits with low power consumption, high degree of randomness (even for a long string of 224  - 1 bits), and high throughput of 1 Mbit s-1 by using MIM devices made of multilayer hexagonal boron nitride (h-BN) is shown. Their application is also demonstrated to produce one-time passwords, which is ideal for the internet-of-everything. The superior stability of the h-BN-based TRNG is related to the presence of few-atoms-wide defects embedded within the layered and crystalline structure of the h-BN stack, which produces a confinement effect that avoids their lateral expansion and results in stable operation.

Electroforming in Metal-Oxide Memristive Synapses.

Memristors have shown an extraordinary potential to emulate the plastic and dynamic electrical behaviors of biological synapses and have been already used to construct neuromorphic systems with in-memory computing and unsupervised learning capabilities; moreover, the small size and simple fabrication process of memristors make them ideal candidates for ultradense configurations. So far, the properties of memristive electronic synapses (i.e., potentiation/depression, relaxation, linearity) have been extensively analyzed by several groups. However, the dynamics of electroforming in memristive devices, which defines the position, size, shape, and chemical composition of the conductive nanofilaments across the device, has not been analyzed in depth. By applying ramped voltage stress (RVS), constant voltage stress (CVS), and pulsed voltage stress (PVS), we found that electroforming is highly affected by the biasing methods applied. We also found that the technique used to deposit the oxide, the chemical composition of the adjacent metal electrodes, and the polarity of the electrical stimuli applied have important effects on the dynamics of the electroforming process and in subsequent post-electroforming bipolar resistive switching. This work should be of interest to designers of memristive neuromorphic systems and could open the door for the implementation of new bioinspired functionalities into memristive neuromorphic systems.

Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory.

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material's microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device's performance and variability to be evaluated, the analog resistance switching to be optimized, and the device's reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

Understanding Current Instabilities in Conductive Atomic Force Microscopy.

: Conductive atomic force microscopy (CAFM) is one of the most powerful techniques in studying the electrical properties of various materials at the nanoscale. However, understanding current fluctuations within one study (due to degradation of the probe tips) and from one study to another (due to the use of probe tips with different characteristics), are still two major problems that may drive CAFM researchers to extract wrong conclusions. In this manuscript, these two issues are statistically analyzed by collecting experimental CAFM data and processing them using two different computational models. Our study indicates that: (i) before their complete degradation, CAFM tips show a stable state with degraded conductance, which is difficult to detect and it requires CAFM tip conductivity characterization before and after the CAFM experiments; and (ii) CAFM tips with low spring constants may unavoidably lead to the presence of a ~1.2 nm thick water film at the tip/sample junction, even if the maximum contact force allowed by the setup is applied. These two phenomena can easily drive CAFM users to overestimate the properties of the samples under test (e.g., oxide thickness). Our study can help researchers to better understand the current shifts that were observed during their CAFM experiments, as well as which probe tip to use and how it degrades. Ultimately, this work may contribute to enhancing the reliability of CAFM investigations.